SoC Hardware Overview Part 1 (OEMB5500)
1 Hour Online Course

Course Description

Learn about the Cyclone® V and Arria® V SoC FPGA hardware, and in particular, the Hard Processor Subsystem (HPS). The online training includes information about the MPU subsystem, including the ARM® Cortex™-A9 processor core, the AMBA® AXI™ bridges, the Level 3 and Level 4 interconnects, and the main memory that is included in the HPS.

At Course Completion

You will be able to:

• Understand the MPU subsystem and Cortex-A9 processor core as implemented in Altera SoC FPGAs
• Understand the AMBA AXI bridge architecture
• Understand the Level 3 interconnect

Skills Required

• Basic knowledge of FPGA architecture

Follow-on Courses

Upon completing this course, we recommend the following courses (in no particular order):

• SoC Hardware Overview Part 2

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

• Embedded HW Designer
• SOC Designer

Class Schedule

Result Showing 1
Location	Dates	Price
On-line	Any Time	Free	Register Now

Request a class in your region