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VHDL Basics
(OHDL1110)
1.5 Hours
Online Course
Course Description
This online course will provide you with an overview of the VHDL language and its use in logic design. By the end of the course, you will understand the basic parts of a VHDL model and how each is used. You will also gain an understanding of the basic VHDL constructs used in both the synthesis and simulation environments. You will also be able to build complete logic structures that can be synthesized into programmable logic device hardware. Lastly, you gain the understanding required to connect entire models together to create hierarchical designs.
At Course Completion
- Understanding the simulation versus synthesis environment
- Using VHDL design units including entities, architectures, configurations and packages
- Building VHDL models using language constructs such as assignment statements, process statements, if statements, case statements and loops
- Creating synthesizable models (behavioral coding style)
- Using VHDL component instantiations to create hierarchy (structural coding style)
Skills Required
- Background in digital logic design
- Prior knowledge of a programming language (e.g., "C" language) is a plus
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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