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Verilog HDL Basics
(OHDL1120)
1 Hour
Online Course
Course Description
This course will provide an overview of the Verilog hardware description language (HDL) and its use in programmable logic design. The emphasis is on the synthesis constructs of Verilog HDL; however, you will also learn about some simulation constructs. You will gain a basic understanding of Verilog HDL that will enable you to begin creating your design. The Quartus® II software v. 8.0 is used for demonstration purposes.
At Course Completion
- Understanding the origin of the Verilog HDL language
- Understanding the language basics
- Using Verilog HDL building blocks (design units) including modules, ports, processes, and assignments
- Ability to model code styles including behavioral code style and structural code style
- Understanding the design methodologies of Verilog HDL and the differences between simulation models and synthesis models
Skills Required
- Background in digital logic design
- Prior knowledge of a programming language (e.g., "C" language) is a plus
- No prior knowledge of Verilog HDL or Quartus II software is required
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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