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Japanese Version: System-on-a-Programmable-Chip Design Using the Nios II Embedded Processor
(OJEMB1110)
1.5 Hours
Online Course
Course Description
This course has Japanese audio. You will learn how easy it is to design in a soft core embedded processor with an Altera FPGA. This course is focused on the development of Nios II hardware and software. You will learn how to integrate a Nios II 32-bit microprocessor and test it in an Altera FPGA. You will learn how to configure and compile designs using the Quartus II software v. 6.1 and SOPC Builder software tools as well as how develop and run embedded software for Nios II in the Nios II IDE. You will learn how to use the Nios II C2H Compiler to create a hardware accelerator from a function in your Nios II C software code.
At Course Completion
- Configure, compile, & verify a Nios II processor design
- Use SOPC Builder to incorporate a custom peripheral & instruction into an embedded system
- Create software projects using the Nios II IDE
- Compile, run, & debug embedded software
- Learn how to access peripherals from C using the Nios II HAL API functions
- Learn how to create a hardware accelerator from a C function using the Nios II C2H Compiler
Skills Required
- Background in digital logic design
- Working knowledge of the Quartus II development software
- Some knowledge of programming in C for embedded systems
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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