Course Description
Memory interface design for FPGAs has traditionally been a complex process. This training will highlight the ease with which high performance memory controllers can be implemented and tested in an Altera FPGA using the Quartus® II software v. 11.0. You’ll learn how to select, parameterize, and test your memory controller IP easily by following a recommended design flow. This training focuses on creating DDR-style memory interfaces using Altera’s UniPHY self-calibrating PHY block. This PHY can be used with Altera’s memory controller IP or combined with your own custom controller.At Course Completion
You will be able to:- Find and parameterize high-performance Altera® memory controller IP
- Instantiate and test high-performance memory controller IP in your design
- Set up and run an RTL simulation in the ModelSim®-Altera Starter Edition software (from within the Quartus II software)
- Perform a static timing analysis with the TimeQuest timing analyzer
- Correct some common timing problems
- Understand the advantages of using the UniPHY auto-calibrated PHY in a design
Prerequisites
We recommend completing the following courses:- External Memory Solutions Overview
- TimeQuest Timing Analyzer
- Using the Quartus II Software: An Introduction
Skills Required
- Background in digital logic design
- Basic knowledge of memory interfaces
- Familiarity with the Quartus II software
- Familiarity with a simulation tool, such as the ModelSim-Altera Starter Edition
- Prior exposure to the TimeQuest timing analysis tool
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
| Result Showing 1 | ||||
|---|---|---|---|---|
| Location | Dates | Price | ||
| On-line | Any Time | Free | Register Now | |
Request a class in your region
