Constraining and Analyzing Double Data Rate Source Synchronous Interfaces (OMEM1120)
1 Hour Online Course

Course Description

This training provides an introduction to double data rate interfaces and some of the challenges involved in constraining them. You’ll learn about clock and data constraints for inputs and outputs, including two methods of making the constraints. You’ll learn about timing exceptions for the interfaces. Finally, you’ll learn how to analyze source synchronous interface timing with the TimeQuest timing analyzer in the Quartus® II software v. 7.1.

At Course Completion

You will be able to:

• Constrain double data rate source synchronous interfaces with SDC constraints
• Analyze timing for double data rate source synchronous interfaces with the TimeQuest timing analyzer

Prerequisites

We recommend completing the following courses:

• TimeQuest Timing Analyzer

Skills Required

• Knowledge of static timing analysis concepts
• Knowledge of source synchronous interface theory
• Completion of “Validating Performance with the TimeQuest Static Timing Analyzer”

Applicable Training Curriculum

This course is part of the following Altera training curriculum:

• HardCopy Designer
• FPGA Designer
• ASIC-to-FPGA Designer

Class Schedule

Result Showing 1
Location	Dates	Price
On-line	Any Time	Free	Register Now

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