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PCI Express Design with Stratix IV GX FPGAs
(OPCI1115)
1.5 Hours
Online Course
Course Description
You will learn how to build PCI Express solutions targeting Stratix® IV GX devices. You will learn about the available PCI Express Hard IP block and how to customize its layers using the Quartus® II software v. 8.0 to create your own PCI Express Gen 1 or Gen 2 design. You will see how to integrate a PCI Express solution into the system interconnect fabric using the SOPC Builder tool for an embedded system implementation. You will also discover the necessary steps to connect your own custom transaction and/or data link layer modules to the built-in Stratix IV GX transceiver Physical Interface for PCI Express (PIPE).
At Course Completion
- Describe the features and functionality of the PCI Express Hard IP block found in Stratix IV GX devices
- Configure a PCI Express solution using the PCI Express Hard IP
- Successfully integrate a PCI Express Hard IP solution into SOPC Builder and describe how it interfaces with the system interconnect
- Configure the Stratix IV GX PHY for a custom PCI Express solution
Prerequisites
We recommend completing the following courses:
Skills Required
- Understanding of the PCI Express Protocol specifications
- Familiarity with common high-speed transceiver architecture OR viewing the online course: "Transceiver Basics"
- Familiarity with FPGA/CPLD design flow
- One of the following:
- Completion of "Using the Quartus II Software: An Introduction" online course
- Completion of "Quartus II Software Design Series: Foundation" instructor-led or online course
- A solid working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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