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Serial RapidIO Design with Stratix IV GX FPGAs
(ORIO1115)
1.5 Hours
Online Course
Course Description
This online course will instruct you in how to build Serial RapidIO solutions targeting Stratix® IV GX FPGAs using the Quartus® II software v. 8.0. In this course, you will learn how to configure the Altera RapidIO MegaCore® IP function for your RapidIO-based design and connect it to the system interconnect fabric using the SOPC Builder tool. You will also learn how to directly configure the Stratix IV GX transceivers for a physical-layer only implementation, so you can connect your own custom RapidIO logical and transport layer blocks.
At Course Completion
- Describe the features and functionality of the RapidIO MegaCore IP function when using the Stratix® IV GX transceivers
- Configure a Serial RapidIO design block and incorporate it into an SOPC Builder system
- Describe how the RapidIO core interfaces with the system interconnect fabric
- Configure the Stratix IV GX transceiver for a custom RapidIO solution
Prerequisites
We recommend completing the following courses:
Skills Required
- Understanding of the RapidIO technology specifications
- Familiarity with common high-speed transceiver architecture OR viewing the online course: "Transceiver Basics"
- Familiarity with FPGA/CPLD design flow
- One of the following:
- Completion of "Using the Quartus II Software: An Introduction" online course
- Completion of "Quartus II Software Design Series: Foundation" instructor-led or online course
- A solid working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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