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Dynamically Reconfiguring Stratix II GX Transceivers
(OSIIGX1110)
1.5 Hours
Online Course
Course Description
You will learn to use the dynamic reconfiguration capability of the Stratix® II GX device family to differentiate your product. By the end of the course, you will be able to indicate the parts of the transceiver block that can be reconfigured dynamically and use FPGA logic to control the reconfiguration circuitry. You will also be able to create a reconfiguration block using the MegaWizard® plug-in within the Quartus® II software v. 7.2 and test your design with the SignalTap® II logic analyzer feature.
At Course Completion
- Indicate the reconfigurable parts of the Stratix II GX transceiver block
- Incorporate the dynamic reconfiguration megafunction, ALT2GXB_RECONFIG, into your transceiver design
- Utilize the dynamic reconfiguration circuitry to change transceiver parameters without reconfiguring the FPGA
- Debug your dynamic reconfiguration logic in-system using the SignalTap II logic analyzer
Prerequisites
We recommend completing the following courses:
Skills Required
- Background in high-speed design, digital logic, and board design
- Working knowledge of FPGA design flow using the Quartus II and ModelSim®-Altera software, including design entry, compilation, simulation and debugging
- Familiarity with the Stratix II GX high-speed transceiver architecture
- Basic familiarity with high-speed serial I/O protocols and standards, such as PCI Express or Gigabit Ethernet
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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