Course Description
This training is an introduction to the reconfiguration capability found in FPGA embedded transceivers. In it, you will learn which transceiver parameters are reconfigurable. You will learn how to configure and connect the transceiver megafunctions to support reconfiguration as well as design your own custom logic to control reconfiguration. You'll see how to control & improve the signal integrity of your board, & as a result, your system, by reconfiguring the input & output buffer settings. The Quartus® II software v. 10.1 will be used for demonstrations.
NOTE: Transceiver reconfiguration in Stratix V, Arria V and Cyclone V device families is covered in the online training "Transceiver Reconfiguration in Altera 28-nm Devices”.
At Course Completion
You will be able to:- Indicate the reconfigurable parts of the gigabit transceiver buffers
- Incorporate the dynamic reconfiguration megafunction, ALTGX_RECONFIG, into your transceiver design
- Utilize the dynamic reconfiguration circuitry to change transceiver PMA settings without reconfiguring the entire FPGA
Prerequisites
We recommend completing the following courses:- The Quartus II Software Design Series: Foundation (Instructor-led / Virtual Training)
- The Quartus II Software Design Series: Foundation (Online Training)
- Transceiver Basics
- Using the Quartus II Software: An Introduction
Skills Required
- Background in high-speed design, digital logic, and board design
- Working knowledge of FPGA design flow using the Quartus II software including design entry, compilation, simulation and debugging
- Familiarity with FPGA high-speed transceiver architecture (e.g Cyclone IV GX, Arria II GX, Stratix IV GX, Stratix IV GT or HardCopy IV GX devices)
- Familiarity with configuring the FPGA high-speed transceivers using the ALTGX megafunction
Applicable Training Curriculum
This course is part of the following Altera training curriculum:Class Schedule
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