Course Description
You will learn tips and tricks to use the Synopsys Synplify Pro software to improve turnaround time, improve quality of results, and aid in design re-use. You will learn about script-based flows and flow automation. You will also learn how to handle Altera® IP (intellectual property) to extract timing information important for synthesis. Finally, you will learn how to best integrate the Quartus® II software with the Synopsys Synplify Pro synthesis software.At Course Completion
You will be able to:- Use a script-based flow to automate your design flow
- Get faster turnaround times
- Boost quality of results
- Integrate intellectual property in your design
- Follow best practices for design constraints
Skills Required
- Background in digital logic design
Applicable Training Curriculum
This course is part of the following Altera training curriculum:- ASIC-to-FPGA Designer
- CPLD Designer
- Embedded HW Designer
- FPGA Designer
- HardCopy Designer
- Transceivers
Class Schedule
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| Location | Dates | Price | ||
| On-line | Any Time | Free | Register Now | |
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