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10/100/1000 Mb & 10Gb Ethernet Design with Stratix IV GX FPGAs
(OTSE1115)
1.5 Hours
Online Course
Course Description
This online course will instruct you in how to build Ethernet solutions targeting Stratix® IV GX FPGAs using the Quartus® II software v. 8.0. In this course, you will learn how to configure the Altera Triple Speed Ethernet (TSE) MegaCore® IP function for your Ethernet-based design and how to connect it to the system interconnect fabric using the SOPC Builder tool. For a 10G Ethernet solution, you will discover how you can use the available 10G Ethernet reference design to help jumpstart your own designs. Lastly, you will investigate how to directly configure the Stratix IV GX transceivers in supported Ethernet modes and connect them to your own custom media access control (MAC) block implemented in FPGA logic.
At Course Completion
- Describe the features and functionality of the TSE MegaCore IP function when using the Stratix IV GX transceivers
- Configure a stand-alone TSE MegaCore implementation and incorporate it into a design
- Incorporate a TSE component into a SOPC Builder system
- Utilize the 10G Ethernet Reference Design to create a custom 10G Ethernet solution
- Configure the Stratix IV GX transceiver for a custom Ethernet MAC solution
Prerequisites
We recommend completing the following courses:
Skills Required
- Understanding of the Ethernet technology specifications
- Familiarity with common high-speed transceiver architecture OR viewing the online course: "Transceiver Basics"
- Familiarity with FPGA/CPLD design flow
- One of the following:
- Completion of "Using the Quartus II Software: An Introduction" online course
- Completion of "Quartus II Software Design Series: Foundation" instructor-led or online course
- A solid working knowledge of the Quartus II software
Applicable Training Curriculum
This course is part of the following Altera training curriculum:
Class Schedule
Request a class in your region
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