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Home > Education & Events > Training Courses > Curriculum > CPLD Designer Print This Page Subscribe to Email CPLD Designer Curriculum A CPLD designer is defined to be a hardware engineer targeting a CPLD (for example, a MAX® II device). Table Legend   Required if no prior experience   Optional   Suggested Instructor-led Training Online Training Introduction to VHDL (IHDL110) (8 hours) or Introduction to Verilog HDL (IHDL120) (8 hours) Basics of Programmable Logic (ODSW1005) (1 hour) The Quartus® II Software Design Series: Foundation (IDSW110) (8 hours) VHDL Basics (OHDL1110) (1 hour) or Verilog HDL Basics (OHDL1120) (1 hour) Advanced VHDL Design Techniques (IHDL240) (8 hours) or Advanced Verilog HDL Design Techniques (IHDL230) (8 hours) The Quartus II Software Interactive Tutorial (ODSW1050) (4 hours) Using the Quartus II Software: An Introduction (ODSW1100) (1.5 hours) 简体中文 (OCDSW1100) or The Quartus II Software Design Series: Foundation (ODSW1110) (8 hours) 简体中文 (OCDSW1110) Using the Quartus II Software: Schematic Design (ODSW1105) (0.5 hours) 简体中文 (OCDSW1105) TimeQuest Timing Analyzer (ODSW1115) (1.5 hours) 简体中文 (OCDSW1115) Rate This Page

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