FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

CPLD Designer Curriculum

Home > Training > Training Courses > Curricula > CPLD Designer

A CPLD designer is defined to be a hardware engineer targeting a CPLD (for example, a MAX® II device).

Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.

Table Legend
  Required if no prior experience
  Optional
  Suggested
Instructor-led Training Online Training
Best Practices for Maximizing FPGA Design Productivity
(IPRO200)

(16 hours)
Read Me First!
(ORMF1000)

(0.5 hours)
简体中文
(OCRMF1000)

(0.5 hours)
Introduction to VHDL
(IHDL110)

(8 hours)
or Introduction to Verilog HDL
(IHDL120)

(8 hours)
MAX IIZ CPLDs in Mobile Handsets
(OMAX1110)

(0.5 hours)
简体中文
(OCMAX1110)

(0.5 hours)
The Quartus® II Software Design Series: Foundation
(IDSW110)

(8 hours)
Basics of Programmable Logic
(ODSW1005)

(1 hour)
简体中文
(OCDSW1005)

(1 hour)
Advanced VHDL Design Techniques
(IHDL240)

(8 hours)
or Advanced Verilog HDL Design Techniques
(IHDL230)

(8 hours)
VHDL Basics
(OHDL1110)

(1.5 hours)
简体中文
(OCHDL1110)

(1 hour)
  Verilog HDL Basics
(OHDL1120)

(1 hour)
简体中文
(OCHDL1120)

(0.5 hours)
    or or
      SystemVerilog with the Quartus II Software
(OHDL1125)

(1 hour)
   
      The Quartus II Software Interactive Tutorial
(ODSW1050)

(4 hours)
Using the Quartus II Software: An Introduction
(ODSW1100)

(1.5 hours)
简体中文
(OCDSW1100)
or The Quartus II Software Design Series: Foundation
(ODSW1110)

(8 hours)
简体中文
(OCDSW1110)
 
Using the Quartus II Software: Schematic Design
(ODSW1105)

(0.5 hours)
简体中文
(OCDSW1105)
or Quartus II V9.0 基礎編-1 SettingsとAssignments (OJDSW1111)
(1 hour)
 
I/O System Design
(ODSW1107)

(2 hours)
Quartus II V9.0 基礎編-2 I/O プランニング
(OJDSW1112)

(0.5 hours)
TimeQuest Timing Analyzer
(ODSW1115)

(2 hours)
简体中文
(OCDSW1115)

(1 hour)
Quartus II V9.0 基礎編-4 タイミング解析( TimeQuest )
(OJDSW1115)

(1 hour)
Managing Metastability with the Quartus II Software
(ODSW1113)

(1 hour)
       
      What’s New in the Quartus II Software Version 9.1
(ODSW1103)

(1 hour)
       
      Overview of Mentor Graphic's ModelSim Software
(ODSW1120)

(1 hour)
Quartus II V9.0 基礎編-5 EDAシミュレーション( ModelSim Altera )
(OJDSW1114)

(0.5 hours)
and/or Simulating Designs with 3rd Party EDA Simulators
(ODSW1122)

(1 hour)
Rate This Page


  • Select a Course
    • Course Catalog
    • Class Schedule
    • Curricula
      • CPLD Designer
      • FPGA Designer
      • ASIC-to-FPGA Designer
      • HardCopy Designer
      • DSP Designer
      • SOC Designer
      • Embedded HW Designer
      • Embedded SW Designer
      • Transceivers
      • Scripting
    • Search Courses
  • Your Training
    • Manage Your Courses
  • About Altera Training
    • Training Types
    • Training Options
    • Training Partners
    • Training Credits
  • Training Support
    • Training FAQ
    • Training Help
    • Altera.com Account Help
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates