A DSP designer is a hardware engineer implementing a digital signal processing (DSP) application using an FPGA. These engineers include engineers and scientists working on DSP modeling, software and hardware implementation and optimizing algorithms on an FPGA architecture.
Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.
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| Required if no prior experience | |
| Optional | |
| Suggested | |
If you wish to target specific features in the FPGA you may wish to go through the FPGA designer curriculum at this point. If your application uses an embedded processor you may wish to go through one of the embedded curriculums at this point.
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| Read Me First! (ORMF1000) (0.5 hours) 简体中文 (OCRMF1000) (0.5 hours) 日本語 (OJRMF1000) (0.5 hours) |
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| Variable-Precision DSP Blocks in Altera 28-nm FPGAs (ODSP1106) (0.5 hours) |
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| Setting up Floating Licenses (ODSW1040) (0.5 hours) |
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| Designing with DSP Builder Advanced Blockset: An Overview (ODSP1115) (1 hour) |
or | DSP Builder Standard Blockset: An Overview (ODSP1110) (1 hour) |
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| Implementing Video Systems (ODSP1118) (1.5 Hours) |
Viterbi Decoder (OVTBI1110) (1 hour) |
Using Cascaded-Integrator- Comb Filter in Multirate Digital Systems (OCIC1110) (1 hour) |
FIR Compiler II (OFIR1100) (0.5 hours) |
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Introduction to Parallel Computing with OpenCL |
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| Writing OpenCL Programs for Altera FPGAs (OOPNCL200) (1 Hour) 简体中文 (OCOPNCL200) (1 Hour) |
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| Running OpenCL on Altera FPGAs (OOPNCL300) (0.5 Hours) 简体中文 (OCOPNCL300) 0.5 Hours |
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| Instructor-led / Virtual Classroom Training | ||
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| Parallel Computing with OpenCL Workshop (IOPNCL110) (8 hours) |
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| Designing with DSP Builder (IDSP210) (8 hours) |
and/ or | Designing with DSP Builder Advanced Blockset (IDSP220) (8 hours) |
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| Introduction to VHDL (IHDL110) (8 hours) |
or | Introduction to Verilog HDL (IHDL120) (8 hours) |
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| The Quartus ® II Software Design Series: Foundation (IDSW110) (8 hours) |
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| Video System Design with the Video and Imaging Processing Framework (IDSP230) (8 Hours) |
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