An embedded hardware designer is a hardware engineer who implements an embedded processor (for example, the Nios® II embedded processor) on an FPGA.
Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.
| Table Legend | |
| Required if no prior experience | |
| Optional | |
| Suggested | |
| Instructor-led / Virtual Classroom Training | ||
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| Parallel Computing with OpenCL Workshop (IOPNCL110) (8 hours) |
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| Introduction to VHDL (IHDL110) (8 hours) |
or | Introduction to Verilog HDL (IHDL120) (8 hours) |
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| The Quartus® II Software Design Series: Foundation (IDSW110) (8 hours) |
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| Advanced VHDL Design Techniques (IHDL240) (8 hours) |
or | Advanced Verilog HDL Design Techniques (IHDL230) 8 hours) |
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| Design Optimization Using Quartus II Incremental Compilation (IDSW142) (8 hours) |
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| Introduction to the Qsys System Integration Tool (IQSYS101) (8 hours) |
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| Designing with the Nios II Processor (IEMB112) (8 hours) |
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| Advanced Qsys System Integration Tool Methodologies (IQSYS102) (8 hours) |
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| Designing with an ARM-based SoC (ISOC101) (8 hours) |
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| Video System Design with the Video and Imaging Processing Framework (IDSP230) (8 hours) |
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