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Home > Education & Events > Training Courses > Curriculum > ASIC-to-FPGA Designer Print This Page Subscribe to Email ASIC-to-FPGA Designer Curriculum This curriculum is designed for hardware engineers with experience designing ASICs and who are familiar with VHDL or Verilog HDL. These engineers are targeting an FPGA (for example, a Stratix® II device). Table Legend   Required if no prior experience   Optional   Suggested Instructor-led Training Online Training The Quartus® II Software Design Series: Foundation (IDSW110) (8 hours) The Quartus II Software Interactive Tutorial (ODSW1050) (4 hours) The Quartus II Software Design Series: Timing Analysis (IDSW120) (8 hours) Using the Quartus II Software: An Introduction (ODSW1100) (1.5 hours) 简体中文 (OCDSW1100) or The Quartus II Software Design Series: Foundation (ODSW1110) (8 hours) 简体中文 (OCDSW1110) The Quartus II Software Design Series: Verification (IDSW130) (8 hours) I/O Management (ODSW1107) (1 hour) The Quartus II Software Design Series: Optimization (IDSW140) (8 hours) TimeQuest Timing Analyzer (ODSW1115) (1.5 hours) 简体中文 (OCDSW1115) Interfacing to External Memory with Altera FPGAs (IMEM210) (8 hours) What’s New in the Quartus II Software Version 8.0 (ODSW1103) (1 hour) Design Planning Guidelines for High-Density FPGAs (ODSW1130) (1 hour) Early Pin Planning with Pin Planner in the Quartus II Software (ODSW1112) (0.5 hours) Stratix III Devices: Features and Capabilities (OSIII1110) (1 hour) or Cyclone III Devices: Features and Capabilities (OCIII1110) (1 hour) Introduction to Incremental Compilation (ODSW1136) (2 hours) Power Analysis with the Quartus II Software (ODSW1146) (1 hour) Using the Quartus II Software: Managing Design Changes with Chip Editor (ODSW1152) (1 hour) Best Practices for Incremental Compilation Partitions and Floorplan Assignments - Part 1 of 2 (ODSW1143) (1 hour) Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction (OVJTAG1110) (0.5 hours) Using the Quartus II Software: Chip Planner (ODSW1155) (1 hour)   Best Practices for Incremental Compilation Partitions and Floorplan Assignments - Part 2 of 2 (ODSW1144) (1 hour) Serial RapidIO Design with Stratix IV GX FPGAs (ORIO1115) (1.5 hours) Using High Performance Memory Interfaces in Altera FPGAs (OMEM1110) (1.5 hours) SignalTap II Embedded Logic Analyzer (ODSW1164) (1.5 hours) 简体中文 (OCDSW1165) Constraining and Analyzing Timing for Source Synchronous Circuits with TimeQuest (ODSW1160) (1 hour)   Constraining and Analyzing Double Data Rate Source Synchronous Interfaces (OMEM1120) (1 hour) Rate This Page

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