FPGA Designer Curriculum

An FPGA designer is a hardware engineer who needs to create and verify a design on an FPGA. This engineer may or may not have prior experience with FPGAs. (see also FPGA Overview).

Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.

Instructor-led Training			Online Training
Best Practices for Maximizing FPGA Design Productivity (IPRO200) (16 hours)			Read Me First! (ORMF1000) (0.5 hours) 简体中文 (OCRMF1000)
Introduction to VHDL (IHDL110) (8 hours)	or	Introduction to Verilog HDL (IHDL120) (8 hours)	Basics of Programmable Logic (ODSW1005) (1 hour) 简体中文 (OCDSW1005) (1 hour) 日本語 (OJDSW1005) (1 hour)
The Quartus® II Software Design Series: Foundation (IDSW110) (8 hours)			How to Begin a Simple FPGA Design (ODSW1010) (1 hour) 简体中文 (OCDSW1010) (1 hour) はじめてのFPGA設計 (OJDSW1010) (1 hour)
			VHDL Basics (OHDL1110) (1.5 hours) 简体中文 (OCHDL1110) (1 hour)   Verilog HDL Basics (OHDL1120) (1 hour) 简体中文 (OCHDL1120) (0.5 hours) or or   SystemVerilog with the Quartus II Software (OHDL1125) (1 hour)
The Quartus II Software Design Series: Timing Analysis (IDSW120) (8 hours)
The Quartus II Software Design Series: Verification (IDSW130) (8 hours)
Interfacing to External Memory with Altera FPGAs (IMEM210) (8 hours)			The Quartus II Software Interactive Tutorial (ODSW1050) (4 hours)
The Quartus II Software Design Series: Optimization (IDSW140) (8 hours)			Using the Quartus II Software: An Introduction (ODSW1100) (1.5 hours) 简体中文 (OCDSW1100)			or	The Quartus II Software Design Series: Foundation (ODSW1110) (8 hours) 简体中文 (OCDSW1110)
Advanced VHDL Design Techniques (IHDL240) (8 hours)	or	Advanced Verilog HDL Design Techniques (IHDL230) 8 hours)	Using the Quartus II Software: Schematic Design (ODSW1105) (0.5 hours) 简体中文 (OCDSW1105)	or	Quartus II V9.0 基礎編-1 SettingsとAssignments (OJDSW1111) (1 hour)
			I/O System Design (ODSW1107) (2 hours) Quartus II V9.0 基礎編-2 I/O プランニング (OJDSW1112) (0.5 hours)
			Advanced I/O System Design (ODSW1108) (1.5 hours) 简体中文 (OCDSW1108) (1.5 hours
			TimeQuest Timing Analyzer (ODSW1115) (2 hours) 简体中文 (OCDSW1115) (1 hour) Quartus II V9.0 基礎編-4 タイミング解析( TimeQuest ) (OJDSW1115) (1 hour)
			Managing Metastability with the Quartus II Software (ODSW1113) (1 hour)
			What’s New in the Quartus II Software Version 9.1 (ODSW1103) (1 hour)
			Overview of Mentor Graphic’s ModelSim Software (ODSW1120) (1 hour) Quartus II V9.0 基礎編-5 EDAシミュレーション( ModelSim Altera ) (OJDSW1114) (0.5 hours)			and/ or	Simulating Designs with 3rd Party EDA Simulators (ODSW1122) (1 hour)
			Switching to the TimeQuest Timing Analyzer (ODSW1125) (1 hour) 简体中文 (OCDSW1125) (1 hour)
			Cyclone IV FPGAs: Features & Capabilities (OCIV1110) (0.5 hours) 简体中文 (OCCIV1110) (0.5 hours) Stratix III Devices: Features and Capabilities (OSIII1110) (1 hour) 40nm Stratix IV FPGAs (OSIV1110) (0.5 hours) 简体中文 (OCSIV1110) (0.5 hours) Cyclone III Devices: Features and Capabilities (OCIII1110) (1 hour)
			Design Planning Guidelines for High-Density FPGAs (ODSW1130) (1 hour)
			Configuring Altera FPGAs (ODEV1100) (2 hours) 简体中文 (OCDEV1100) (2 hours)
			Introduction to Incremental Compilation (ODSW1136) (2.5 hours)	Power Analysis with the Quartus II Software (ODSW1146) (1 hour)					Using the Quartus II Software: Chip Planner (ODSW1155) (1.5 hours)
			SignalTap II Embedded Logic Analyzer (ODSW1164) (2 hours) 简体中文 (OCDSW1165) (1 hour)	Power Distribution Network Design for Stratix III and Stratix IV (OPDN1100) (0.5 hours) 简体中文 (OCPDN1100) (0.5 hours)					External Memory Solutions Overview (OMEM1109) (0.5 hours)
			SignalTap II Logic Analyzer: New Features in Quartus II Software 9.0 (ODSW1169) (0.5 hours)	Power Distribution Network Design Using Altera PDN Design Tools (OPDN1105) (0.5 hours)					Using High Performance Memory Interfaces in Altera FPGAs (OMEM1110) (2 hours)
			Best HDL Design Practices for Timing Closure (OHDL1130) (1 hour)	Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction (OVJTAG1110) (0.5 hours)					Constraining and Analyzing Timing for Source Synchronous Circuits with TimeQuest (ODSW1160) (1 hour)
			Timing Closure Using Quartus II Advisors and Design Space Explorer (ODSW1141) (1 hour) 简体中文 (OCDSW1141) (1 hour)						Constraining and Analyzing Double Data Rate Source Synchronous Interfaces (OMEM1120) (1 hour)
			Timing Closure Using Quartus II Physical Synthesis Optimizations (ODSW1139) (1 hour) 简体中文 (OCDSW1139) (1 hour)