FPGA Designer Curriculum

An FPGA designer is a hardware engineer who needs to create and verify a design on an FPGA. This engineer may or may not have prior experience with FPGAs. (see also FPGA Overview).

Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.

Table Legend
	Required if no prior experience
	Optional
	Suggested

Online Training
Instructor-led/Virtual Classroom Training

Online Training

Read Me First!
(ORMF1000)
(0.5 hours)
简体中文
(OCRMF1000)
(0.5 hours)
日本語
(OJRMF1000)
(0.5 hours)

Setting up Floating Licenses
(ODSW1040)
(0.5 hours)

Basics of Programmable Logic
(ODSW1005)
(1.5 hours)
简体中文
(OCDSW1005)
(1 hour)
日本語
(OJDSW1005)
(1 hour)

How to Begin a Simple FPGA Design
(ODSW1010)
(1 hour)
简体中文
(OCDSW1010)
(1 hour)
日本語
(OJDSW1010)
(1 hour)


VHDL Basics (OHDL1110) (1.5 hours) 简体中文 (OCHDL1110) (1 hour)		Verilog HDL Basics (OHDL1120) (1 hour) 简体中文 (OCHDL1120) (0.5 hours)
	or	or
		SystemVerilog with the Quartus II Software (OHDL1125) (1 hour) 简体中文 (OCHDL1125) (1 hour 日本語 (OJHDL1125) (0.5 hours))

Good High-Speed Design Practices
(ODSWTC01)
(0.5 hours)

Synplify Pro Tips and Tricks
(OSYN1100)
(1 hour)

and/
or

Synplify Synthesis Techniques with the Quartus II Software
(OSYN1150)
(0.5 hours)

Creating Reusable Design Blocks
(OIPR1000)
(1.5 hours)

The Quartus II Software Interactive Tutorial
(ODSW1050)
(4 hours)

Using the Quartus II Software: An Introduction
(ODSW1100)
(1.5 hours)
简体中文
(OCDSW1100)
日本語
(OJDSW1100)
(2 hours)

The Quartus II Software Design Series: Foundation
(ODSW1110)
(8 hours)
简体中文
(OCDSW1110)

Using the Quartus II Software: Schematic Design
(ODSW1105)
(0.5 hours)
简体中文
(OCDSW1105)

Quartus II V9.0 基礎編-1 SettingsとAssignments (OJDSW1111)
(1 hour)

I/O System Design
(ODSW1107)
(2 hours)
日本語
(OJDSW1112)
(0.5 hours)
简体中文
(OCDSW1107)
(2 hours)

Advanced I/O System Design
(ODSW1108)
(1.5 hours)
简体中文
(OCDSW1108)
(1.5 hours

TimeQuest Timing Analyzer
(ODSW1115)
(2 hours)
简体中文
(OCDSW1115)
(2 hours)
日本語
(OJDSW1115) (OJFDSW1115)
(0.5 hours) (2 hours)

Constraining Source Synchronous Interfaces
(OCSS1000)
(1 hour)

Constraining Double Data Rate Source Synchronous Interfaces
(ODDR1000)
(0.5 hours)

Timing Closure Using TimeQuest Custom Reporting
(OTIM1100)
(0.5 hours)

Managing Metastability with the Quartus II Software
(ODSW1113)
(1 hour)

What's New in the Quartus II Software
(ODSW1103)
(0.5 hours)
日本語
(OJDSW1103)
(0.5 hours)

Overview of Mentor Graphic's ModelSim Software
(ODSW1120)
(1 hour)
日本語
(OJDSW1120)
(1 hour)

and/
or

Simulating Designs with 3rd Party EDA Simulators
(ODSW1122)
(1 hour)

Power Analysis and Optimization
(ODSWPWR1)
(1.5 hours)
简体中文
(OCDSWPWR1)
(1.5 hours)

Introduction to Qsys
(OQSYS1000)
(1.5 hour)
日本語
(OJQSYS1000)
(1 hour)

Advanced System Design Using Qsys
(OQSYS2000)
(1 hour)

System Console
(OEMB1117)
(1 hour)
简体中文
(OCEMB1117)
(0.5 hours)

Configuring Altera FPGAs
(ODEV1100)
(2 hours)
简体中文
(OCDEV1100)
(2 hours)

Introduction to Incremental Compilation
(ODSW1136)
(3 hours)
简体中文
(OCDSW1136)
(2.5 Hours)
日本語
(OJDSW1136)
(2.5 Hours)

Power Distribution Network Design for Stratix III and Stratix IV
(OPDN1100)
(0.5 hours)
简体中文
(OCPDN1100)
(0.5 hours)

Using the Quartus II Software: Chip Planner
(ODSW1155)
(1 hour)

Quartus II インクリメンタル・コンパイルによるチームベースのデザイン・フロー
(OJDSW1137)
(1 Hour)

Power Distribution Network Design Using Altera PDN Design Tools
(OPDN1105)
(0.5 hours)

External Memory Solutions Overview
(OMEM1109)
(0.5 hours)

SignalTap II Embedded Logic Analyzer: Getting Started
(ODSW1164)
(2 hours)
简体中文
(OCDSW1164)
(2 hours)
日本語
(OJDSW1164)
(2 Hours)

Debugging & Communicating with an FPGA Using the Virtual JTAG Megafunction
(OVJTAG1110)
(0.5 hours)

Using High Performance Memory Interfaces in Altera FPGAs
(OMEM1110)
(2 hours)

Best HDL Design Practices for Timing Closure
(OHDL1130)
(1 hour)
简体中文
(OCHDL1130)
(1 hour)
日本語
(OJHDL1130)
(1 hour)

Debugging JTAG Chain Integrity
(ODJTAG1110)
(0.5 hours)

Design Evaluation for Timing Closure
(ODSWTC02)
(1 hour)

Timing Closure Using Quartus II Advisors and Design Space Explorer
(ODSW1141)
(1 hour)
简体中文
(OCDSW1141)
(1 hour)

Partial Reconfiguration
(OPR100)
(1.5 hours)

Timing Closure Using Quartus II Physical Synthesis Optimizations
(ODSW1139)
(1 hour)
简体中文
(OCDSW1139)
(1 hour)

Instructor-led / Virtual Classroom Training
Introduction to VHDL (IHDL110) (8 hours)	or	Introduction to Verilog HDL (IHDL120) (8 hours)

The Quartus^® II Software Design Series: Foundation (IDSW110) (8 hours)

The Quartus II Software Design Series: Timing Analysis (IDSW120) (8 hours)

Advanced Timing Analysis with TimeQuest (IDSW125) (8 hours)

Introduction to the Qsys System Integration Tool (IQSYS101) (8 hours)

Advanced Qsys System Integration Tool Methodologies (IQSYS102) (8 hours)

The Quartus II Software Debug and Analysis Tools (IDSW135) (8 hours)

Implementing, Simulating and Debugging External Memory Interfaces (IMEM210) (8 hours)

Timing Closure with the Quartus II Software (IDSW145) (8 hours)	and/or	Design Optimization Using Quartus II Incremental Compilation (IDSW142) 8 hours)

Advanced VHDL Design Techniques (IHDL240) (8 hours)	or	Advanced Verilog HDL Design Techniques (IHDL230) 8 hours)

Partial Reconfiguration with Altera FPGAs (IPR100) (8 hours)

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