This curriculum is designed for hardware engineers with experience designing ASICs and who are familiar with VHDL or Verilog HDL. These engineers are targeting a HardCopy® ASIC.
Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.
|Required if no prior experience|
|Instructor-led / Virtual Classroom Training|
|The Quartus® II Software Design Series: Foundation
|The Quartus II Software Design Series: Timing Analysis
|Advanced Timing Analysis with TimeQuest
|The Quartus II Software Debug and Analysis Tools
|Timing Closure with the Quartus II Software
|and/or||Design Optimization Using Quartus II Incremental Compilation