Transceivers Curriculum

A Transceivers/High-Speed I/O Protocol designer is a hardware engineer designing with multi-gigabit transceivers. This person could also be designing the PCB for the FPGA and needs to solve signal integrity issues.

Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.

Instructor-led Training				Online Training
Best Practices for Maximizing FPGA Design Productivity (IPRO200) (16 hours)				Read Me First! (ORMF1000) (0.5 hours) 简体中文 (OCRMF1000)
Introduction to VHDL (IHDL110) (8 hours)	or	Introduction to Verilog HDL (IHDL120) (8 hours)		Basics of Programmable Logic (ODSW1005) (1 hour) 简体中文 (OCDSW1005) (1 hour) 日本語 (OJDSW1005) (1 hour)
The Quartus® II Software Design Series: Foundation (IDSW110) (8 hours)				How to Begin a Simple FPGA Design (ODSW1010) (1 hour) 简体中文 (OCDSW1010) (1 hour) はじめてのFPGA設計 (OJDSW1010) (1 hour)
The Quartus II Software Design Series: Timing Analysis (IDSW120) (8 hours)				VHDL Basics (OHDL1110) (1.5 hours) 简体中文 (OCHDL1110) (1 hour)		Verilog HDL Basics (OHDL1120) (1 hour) 简体中文 (OCHDL1120) (0.5 hours)
					or	or
The Quartus II Software Design Series: Verification (IDSW130) (8 hours)						SystemVerilog with the Quartus II Software (OHDL1125) (1 hour)
Interfacing to External Memory with Altera FPGAs (IMEM210) (8 hours)				The Quartus II Software Interactive Tutorial (ODSW1050) (4 hours)
				Using the Quartus II Software: An Introduction (ODSW1100) (1.5 hours) 简体中文 (OCDSW1100) or The Quartus II Software Design Series: Foundation (ODSW1110) (8 hours) 简体中文 (OCDSW1110) Quartus II V9.0 基礎編-1 Settings と Assignments (OJDSW1111) (1 hour) I/O System Design (ODSW1107) (2 hours) Quartus II V9.0 基礎編-2 I/O プランニング (OJDSW1112) (0.5 hours Advanced I/O System Design (ODSW1108) (1.5 hours) 简体中文 (OCDSW1108) (1.5 hours) TimeQuest Timing Analyzer (ODSW1115) (2 hours) 简体中文 (OCDSW1115) Quartus II V9.0 基礎編-4 タイミング解析( TimeQuest ) (OJDSW1115) (1 hour)
The Quartus II Software Design Series: Optimization (IDSW140) (8 hours)
Advanced VHDL Design Techniques (IHDL240) (8 hours)	or	Advanced Verilog HDL Design Techniques (IHDL230) 8 hours)
				What’s New in the Quartus II Software Version 9.1 (ODSW1103) (1 hour)
				Overview of Mentor Graphic's ModelSim Software (ODSW1120) (1 hour) Quartus II V9.0 基礎編-5 EDAシミュレーション( ModelSim Altera ) (OJDSW1114) (0.5 hours)	and/ or	Simulating Designs with 3rd Party EDA Simulators (ODSW1122) (1 hour)
				Using SOPC Builder (OEMB1115) (1 hour) 简体中文 (OCEMB1115) (1 hour)
				40nm Stratix IV FPGAs (OSIV1110) (0.5 hours) 简体中文 (OCSIV11100) (0.5 hours)		Cyclone IV FPGAs: Features & Capabilities (OCIV1110) (0.5 hours) 简体中文 (OCCIV1110) (0.5 hours)
				Transceiver Basics (OSIIGX1115) (0.5 hours) 简体中文 (OCEMB1115) (0.5 hours)
				External Memory Solutions Overview (OMEM1109) (0.5 hours)
				Using High Performance Memory Interfaces in Altera FPGAs (OMEM1110) (2 hours)
				Protocol-Specific Training (please see table below for more details)
				Dynamically Reconfiguring Stratix II GX Transceivers (OSIIGX1110) (1.5 hours)		Dynamic Reconfiguration in Altera Transceiver Devices (O40NM1000) (1.5 hours)
					or
						Multi-Rate & Multi-Protocol Design with 40nm Devices (O40NM1001) (1.5 hours)
				Power Distribution Network Design for Stratix III and Stratix IV (ODPN1100) (0.5 hours) 简体中文 (OCPDN1100) (0.5 hours)
				Power Distribution Network Design Using Altera PDN Design Tools (OPDN1105) (0.5 hours)

Protocol-Specific Training