SOC Designer Curriculum

A SOC (System-on-Chip) designer is an engineer with either hardware or software design experience who needs to implement their next embedded system on a programmable chip.

Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.

Instructor-led Training		Online Training
Best Practices for Maximizing FPGA Design Productivity (IPRO200) (16 hours)		Read Me First! (ORMF1000) (0.5 hours) 简体中文 (OCRMF1000)
Designing with the Nios® II Processor and SOPC Builder (IEMB115) (16 hours)		Developing Software for the Nios II Processor: Tools Overview (OEMB1120) (0.5 hours) 简体中文 (OCEMB1120) (0.5 hours)	and/ or	Industrial Ethernet Solutions (OIES1110) (0.5 hours) 简体中文 (OCIES1110) (0.5 hours)
Developing Software for Nios II Processor (IEMB230) (16 hours)		Developing Software for the Nios II Processor: Design Flow (OEMB1125) (0.5 hours) 简体中文 (OCEMB1125) (0.5 hours)
		Using the Nios II Processor (OEMB1110) (1.5 hours) 简体中文 (OCEMB1110) (1.5 hours) 日本語 (OJEMB1110) (2.5 hours)	or	Designing with the Nios II Processor and SOPC Builder - Day 1 (OEMB1116) (8 hours)
		Using SOPC Builder (OEMB1115) (1 hour) 简体中文 (OCEMB1115)
		Custom Components for SOPC Builder (OEMB1111) (1.5 hours)
		System Console Overview (OEMB1117) (0.5 hours) 简体中文 (OCEMB1117) (0.5 hours)
		Developing Software for the Nios II Processor: Nios II Software Build Tools for Eclipse (OEMB1128) (0.5 hours)
		Developing software for the NIOS II Processor: MMU & MPU (OEMB1129) (0.5 hours) 简体中文 (OCEMB1129) (0.5 hours)