A SOC (System-on-Chip) designer is an engineer with either hardware or software design experience who needs to implement their next embedded system on a programmable chip.
Before taking this curriculum, Altera recommends reviewing the Design and Support Resources Guide as a starting place to get an overview of all of the collateral, tools, training, resources, and support available to help you throughout your design cycle. If you are new to programmable logic, this guide will help you quickly get started with Altera.
| Table Legend | |
| Required if no prior experience | |
| Optional | |
| Suggested | |
| Instructor-led / Virtual Classroom Training |
|---|
| Best Practices for Maximizing FPGA Design Productivity (IPRO200) (16 hours) |
 |
| Introduction to the Qsys System Integration Tool (IQSYS101) (8 hours) |
|
| Designing with the Nios® II Processor (IEMB112) (8 hours) |
|
| Advanced Qsys System Integration Tool Methodologies (IQSYS102) (8 hours) |
|
| Developing Software for Nios II Processor (IEMB230) (16 hours) |
