Training Partner Profile: Doulos
Overview
Doulos develops and delivers global training solutions for system on a chip (SoC), FPGA and ASIC design and verification. The Altera Professional Designer™ Program from Doulos addresses critical design needs, delivering the best combination of HDL design flow, tool and technology training modules to enable you to optimize your Altera® product-based designs.
Doulos know-how has contributed to the success of more than 600 companies across 35 countries through in-house training and a regular schedule of classes in the United States and Europe. Doulos specializes in language-based design and verification, design flows and methodologies for FPGA, SoC and embedded systems and provides language and methodology training in VHDL, Tcl/Tk, SystemC, PSL, and SystemVerilog.
The training capability of Doulos, with its training partners worldwide, covers all market segments and provides an independent perspective for design languages and methodologies—VHDL, Verilog, SystemC, ARM® SoC Design, SystemVerilog, PSL, e, Tcl/Tk and Perl. Global delivery of training and consultancy is provided in the context of your tools and technology focus.
Instructor-Led Training
Doulos conducts in-house training for clients worldwide and offers the following instructor-led courses in Austria, Belgium, Denmark, Finland, France (in partnership with ALSE), Germany, Ireland, Norway, the Netherlands, Sweden, Switzerland, the United Kingdom and the United States.
| Course Title |
Description |
| Designing with Quartus II Software |
Covers all the main features and capabilities of Quartus® II design software in-depth, including pin planner, device I/O assignments, clock and I/O constraints assignment , and analysis of clock and I/O timing to develop an FPGA or CPLD. Plus, major aspects of the design flow including floorplanning, static timing analysis, power analysis, and design flow automation. |
| Nios II Processors and SoC Designs |
Addresses both hardware and software aspects to enable successful use of Nios® II embedded processors and team work on SoC designs. Includes an appreciation of the hardware platform, hardware-software partitioning, hardware acceleration as well as software development and debugging. |
| VHDL for Altera FPGAs |
Covers the VHDL high-level hardware description and design language, and its use in programmable logic design, including coding for RTL synthesis, exploiting architectural features of the target Altera device, writing test benches and using VHDL tools and the VHDL design flow. Delegates take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects. |
| Advanced VHDL (Complex FPGAs) |
Prepares engineers for complex FPGA or ASIC design, focusing on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches. |
| Expert VHDL Design and Verification |
Focuses on language and synthesis issues, design re-use, test benches and the latest techniques for verification—including an introduction to PSL and modern assertion-based approaches to verification. |
Contact Information
Doulos Headquarters
Church Hatch
22 Market Place
Ringwood, Hampshire
BH24 1AW
United Kingdom
Phone: +44 (0)1425 471223
Fax: +44 (0)1425 471573
Email: info@doulos.com
http://www.doulos.com/altera
Doulos North America
16165 Monterey Road
Suite 109
Morgan Hill, CA 95037
USA
Phone: 1-888-GO-DOULOS
Fax: 1-408-776-8675
Doulos Central Europe
Garbsener Landstr. 10
30419
Hannover, Germany
Phone: +49 (0)511 277 1340
Fax: +49 (0)511 277 1349
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