| Course Title |
Description |
| Quartus II Software and FPGA Architecture Workshop |
This workshop covers all the capabilities of the industry-leading Quartus® II design software. The second part of the workshop provides you with a foundation of knowledge of the Stratix® FPGA and Cyclone® FPGA architectures and how to design for them. |
| VHDL Workshop |
This three-day workshop is a general introduction to the VHDL high-level hardware description and design language, and its use in programmable logic design. |
| System-On-Chip and Nios II Embedded Processor Workshop |
This workshop shows how easy it is to design in a Nios® II processor with an Altera® FPGA. This workshop is focused on the hands-on development of Nios II hardware and software. You will learn how to integrate a Nios II 32-bit microprocessor and test it using an Altera FPGA. |
The Quartus II Software Design Series:
Foundation |
Learn the basics of Quartus II design software, including pin planner, device I/O assignments, clock and I/O constraints assignment, and analysis of clock and I/O timing to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, compile and analyze the results using the TimeQuest timing analyzer in Quartus II software. |
The Quartus II Software Design Series:
Verification |
Explore the advanced features of Quartus II software, including SignalTap® II, ModelSim®, incremental design changes, in-system memory content editor, and embedded logic analyzer that will enable you to verify your FPGA design. |
The Quartus II Software Design Series:
Timing Analysis |
You will learn how to constrain and analyze a design for timing using the TimeQuest timing analyzer in the Quartus II software. |
The Quartus II Software Design Series:
Optimization |
Learn how to shorten your design cycle as well as improve your design performance and utilization using the LogicLock™ regions, incremental compilation, top-down and bottom-up design flows, HDL coding styles, design space explorer, and power consumption reduction features of Quartus II software. |
| Developing Software for the Nios II Processor |
This course is targeted for software engineers and developers. You will learn to develop and run embedded software for the Nios II processor in the Nios II Integrated Development Environment (IDE). You will also be exposed to a few hardware concepts including how a Nios II 32-bit microprocessor is configured and integrated into an Altera FPGA using the Quartus II software and SOPC Builder design tools. |
| Introduction to VHDL |
This one-day course is a general introduction to the VHDL high-level hardware description and design language, and its use in programmable logic design. The emphasis is on the synthesis constructs of VHDL. |
| Advanced VHDL Design Techniques |
You will learn efficient coding techniques for VHDL synthesis, particularly for Altera devices. |
| Introduction to Verilog HDL |
Learn how to implement basic constructs and modeling structures in the Verilog HDL high-level hardware description and design language to create an optimal FPGA design. |
| Advanced Verilog Design Techniques |
In this course, you will learn efficient coding techniques for writing synthesizable Verilog, particularly for Altera devices. |
| Designing with HardCopy II Devices |
This course will teach you how to implement a HardCopy® II ASIC using a Stratix II device as a prototyping vehicle. |
| Designing with Stratix III FPGAs |
This course will teach you how to design with Stratix III FPGAs. You will learn how to use Stratix III architectural features, intellectual property (IP), and new power innovations to build Stratix III FPGA-based systems. |
| Designing with Stratix II FPGAs |
This course will provide you with a foundation of knowledge of Stratix II FPGAs and how to design for them using the Quartus II software. |
| High-Speed Design Using Stratix II GX FPGAs |
In this advanced course, you will implement your own custom high-speed serial I/O protocol using Stratix II GX FPGA multi-gigabit transceivers in basic mode configuration. You will learn transceiver architectural details, transceiver feature settings and design techniques to optimize your high-speed serial link. |
| Accelerating Software Using the Nios II C2H Compiler |
This course will teach you how to accelerate your Nios II software using the Nios II C-to-Hardware (C2H) acceleration compiler. |
| Interfacing to External Memory with Altera FPGAs |
You will implement external memory interfaces with Altera FPGAs and Quartus II software. You will learn the design flows and how to overcome challenges you will face. Since double data rate (DDR) interfaces are most prevalent, the course will focus on DDR 1, 2, and 3. |
| Implementing DSP Designs in FPGAs |
Learn the FPGA design flow for implementing digital signal processing (DSP) designs. You will use DSP Builder which is an interface between the Quartus II software and the MATLAB and Simulink products from The MathWorks. |
| Advanced DSP Design: Using FPGAs to Architect and Optimize a Video and Image Processing System |
Learn to design and integrate a video and image processing system on an Altera FPGA by using Altera IP cores and system-level design tools, including MATLAB/Simulink. |
| Advanced DSP Design: Using FPGAs to Architect and Optimize a Communication System |
Learn to use FPGAs, IP cores, and DSP design tools to implement a high-speed modem design. |
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