Altera's Nios® II family of embedded processors features a general-purpose RISC CPU architecture designed to address a wide range of embedded applications.
The Nios II family consists of three cores: fast (Nios II/f), standard (Nios II/s), and economy (Nios II/e). While each core is optimized for a specific performance and size range, all three share a common 32-bit instruction set architecture (ISA) and are 100 percent binary code-compatible. Students can easily add Nios II processors to their systems by using the SOPC Builder tool featured in the Quartus® II Web Edition development software and the full-featured Quartus II Subscription Edition software.
The Nios II processor is available for download.
Using Embedded Processors
One of the biggest challenges embedded system developers face today is selecting a processor that fits their application requirements. With literally hundreds of embedded processors available—each with a different set of peripherals, memories, interfaces, and performance characteristics—designers often end up either buying more processor than they need (to get the right mix of peripherals, interfaces, etc.) or settling for a less-than-ideal solution to keep costs down.
In addressing these real-world challenges as well as the meeting goal of utilizing a flexible design environment for academic study, students can use Nios II soft processors to create a "perfect fit" in terms of processors, peripherals, memory interfaces, performance characteristics, and cost. This is accomplished by using an Altera® FPGA to create a custom system-on-chip (SoC) or, more accurately, a system-on-a-programmable-chip (SOPC). Students designing SOPCs enjoy tremendous versatility in product feature, performance, cost, and life-cycle management.
Lab Exercises for Embedded System Development
Altera is currently developing a set of laboratory exercises that illustrate system development using SOPC Builder and Nios II processors. For details, check the list of available tutorials and lab exercises.
