Announcements
The current version of the Altera Design Suite is available for downloading from the Download Center. Previous versions are available for download from the Design Software Archives.
The University Program simulation tools, QSim and the Waveform Editor, are bundled with the Quartus II software as of version 11.1. Please visit the Quartus II Simulator page, for more information regarding Qsim and the Waveform Editor.
Quartus® II design software is Altera®'s primary development system. It provides a comprehensive environment for digital design and is an ideal platform for learning both basic and advanced design techniques.
Altera provides the Quartus II Web Edition software, which can be downloaded and used free of charge. This software includes the Nios II soft processor and the SOPC Builder tool.
A licensed commercial version of the Quartus II Subscription Edition software is available for installation in university laboratory facilities.
SOPC Builder and Qsys System Integration Tools
The SOPC Builder and Qsys System Integration software are tools for designing and implementing embedded computer systems. It facilitates modular design by making use of IP cores such as the Nios II processor, memory interfaces, and a variety of I/O interfaces.
The following table shows the available tutorials. Some tutorials exist in multiple versions, dependent on a hardware description language (Verilog or VHDL), development board, and a Quartus II version. Use the filters below to choose the ones that are appropriate for your course.
| Filter Materials | |||
| Choose HDL: | Choose Board: | Choose Quartus II Version: | |
| Table 1. Quartus II Tutorials for Quartus II 12.1 | |
| Title | Downloads |
|---|---|
| Quartus II Tutorials | |
| Quartus II Introduction Using Schematic Designs | |
| Quartus II Introduction | |
| Quartus II Introduction | |
| Using the Library of Parameterized Modules (LPM) | |
| Using the Library of Parameterized Modules (LPM) | |
| Using TimeQuest Timing Analyzer | PDF Design Files |
| Introduction to Quartus II Simulation | |
| Introduction to Quartus II Simulation | |
| Signal Tap II Logic Analyzer | |
| Signal Tap II Logic Analyzer | |
| Debugging of Verilog Hardware Designs | |
| Debugging of VHDL Hardware Designs | |
| SOPC Builder Tutorials | |
| Introduction to the Altera Qsys System Integration Tool | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0-Nano Boards | |
| Using the SDRAM on Altera's DE0-Nano Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Table 1. Quartus II Tutorials for Quartus II 12.0 | |
| Title | Downloads |
|---|---|
| Quartus II Tutorials | |
| Quartus II Introduction Using Schematic Designs | |
| Quartus II Introduction | |
| Quartus II Introduction | |
| Using the Library of Parameterized Modules (LPM) | |
| Using the Library of Parameterized Modules (LPM) | |
| Using TimeQuest Timing Analyzer | |
| Introduction to Quartus II Simulation | |
| Introduction to Quartus II Simulation | |
| Signal Tap II Logic Analyzer | |
| Signal Tap II Logic Analyzer | |
| Debugging of Verilog Hardware Designs | |
| Debugging of VHDL Hardware Designs | |
| Qsys System Integration Tool Tutorials | |
| Introduction to the Altera Qsys System Integration Tool | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0-Nano Boards | |
| Using the SDRAM on Altera's DE0-Nano Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Table 1. Quartus II Tutorials for Quartus II 11.1 | |
| Title | Downloads |
|---|---|
| Quartus II Tutorials | |
| Quartus II Introduction Using Schematic Designs | |
| Quartus II Introduction | |
| Quartus II Introduction | |
| Using the Library of Parameterized Modules (LPM) | |
| Using the Library of Parameterized Modules (LPM) | |
| Using TimeQuest Timing Analyzer | |
| Introduction to Quartus II Simulation | |
| Introduction to Quartus II Simulation | |
| Signal Tap II Logic Analyzer | |
| Signal Tap II Logic Analyzer | |
| Debugging of Verilog Hardware Designs | |
| Debugging of VHDL Hardware Designs | |
| SOPC Builder Tutorials | |
| Introduction to the SOPC Builder | |
| Introduction to the SOPC Builder | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0-Nano Boards | |
| Using the SDRAM on Altera's DE0-Nano Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Table 1. Quartus II Tutorials for Quartus II 11.0 | |
| Title | Downloads |
|---|---|
| Quartus II Tutorials | |
| Quartus II Introduction Using Schematic Designs | |
| Quartus II Introduction | |
| Quartus II Introduction | |
| Using the Library of Parameterized Modules (LPM) | |
| Using the Library of Parameterized Modules (LPM) | |
| Using TimeQuest Timing Analyzer | |
| Introduction to Quartus II Simulation | |
| Introduction to Quartus II Simulation | |
| Signal Tap II Logic Analyzer | |
| Signal Tap II Logic Analyzer | |
| Debugging of Verilog Hardware Designs | |
| Debugging of VHDL Hardware Designs | |
| SOPC Builder Tutorials | |
| Introduction to the SOPC Builder | |
| Introduction to the SOPC Builder | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0-Nano Boards | |
| Using the SDRAM on Altera's DE0-Nano Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Table 1. Quartus II Tutorials for Quartus II 10.1 | |
| Title | Downloads |
|---|---|
| Quartus II Tutorials | |
| Quartus II Introduction Using Schematic Designs | |
| Quartus II Introduction | |
| Quartus II Introduction | |
| Using the Library of Parameterized Modules (LPM) | |
| Using the Library of Parameterized Modules (LPM) | |
| Using TimeQuest Timing Analyzer | |
| Introduction to Simulation | |
| Introduction to Simulation | |
| Signal Tap II Logic Analyzer | |
| Signal Tap II Logic Analyzer | |
| Debugging of Verilog Hardware Designs | |
| Debugging of VHDL Hardware Designs | |
| SOPC Builder Tutorials | |
| Introduction to the SOPC Builder | |
| Introduction to the SOPC Builder | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Table . Quartus II Tutorials for Quartus II 9.0 and 9.1 | |
| Title | Downloads |
|---|---|
| Quartus II Tutorials | |
| Quartus II Introduction Using Schematic Design | |
| Quartus II Introduction | |
| Quartus II Introduction | |
| Using the Library of Parameterized Modules (LPM) | |
| Using the Library of Parameterized Modules (LPM) | |
| Timing Considerations | |
| Timing Considerations | |
| Using TimeQuest Timing Analyzer | |
| Quartus II Simulation | |
| Quartus II Simulation | |
| Signal Tap II Logic Analyzer | |
| Signal Tap II Logic Analyzer | |
| Debugging of Verilog Hardware Designs | |
| Debugging of VHDL Hardware Designs | |
| SOPC Builder Tutorials | |
| Introduction to the SOPC Builder | |
| Introduction to the SOPC Builder | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE0 Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE1 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-70 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
| Using the SDRAM on Altera's DE2-115 Boards | |
