Accelerate IPTV Headend Design Using Available IP and Reference Designs Net Seminar
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On-Demand and Available Now!
Featured Technology: Stratix® II
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Overview
There’s no need to reinvent the wheel to design an IPTV headend. Many key building blocks from video encoders and data communication applications are available and can be reused. They can easily be implemented into FPGAs that are packed with powerful logic, DSP blocks, and memory.
This net seminar describes how using FPGAs with IP and reference designs can accelerate your designs and shorten time to market.
You'll learn how to:
- Design an IPTV headend system
- Integrate the building blocks in your existing systems
- Speed your system design and time-to-market with FPGAs and megafunctions
- Accelerate system performance with optimized IP and reference designs
Who Should View
- System architects
- Embedded system design engineers
- FPGA developers
- Engineering and technical managers
Presenter
Tam Do
Senior Technical Marketing Manager,
Broadcast/Automotive/Consumer Business Unit
As senior technical marketing manager of the Broadcast/Consumer Applications Business Unit, Tam Do is responsible for all technical and marketing issues related to the digital broadcast, automotive, and consumer electronics industries. Mr. Do joined Altera in June 2003. Prior to that, his most recent position was application design manager of LSI Logic’s Consumer Product Group, where his focus was the development design of application-specific standard products (ASSPs) evaluation system and software for the set-top box industry. Mr. Do holds a BSEE from the University of Nevada Reno, and has nearly twenty years of electronics system experience with LSI Logic, Stratex Network, and Verizon Corporation.
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