FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

Building High-Speed FPGA Memory Interfaces

Home > Training > Webcasts & Videos > All Webcasts & Series > Building High-Speed FPGA Memory Interfaces


Available Now, On-Demand
Length
: 15 minutes

Designing large, parallel, high-frequency external memory interfaces is not an easy task, but new FPGA technologies can help ensure that your system will succeed with maximum memory bandwidth. 

 

View this webcast to learn:

  • Explore new 40-nm FPGA architectures built for reliable high-speed memory interface operation
  • See how to use IP to quickly and easily build memory interfaces
  • Learn how soft IP buys back timing margin by reducing or eliminating process, voltage and temperature timing variations
  • See the signal quality achieved using these techniques

Presenter: Paul Evans
Product Marketing Manager

View Free Webcast


 

Rate This Page


  • Webcasts
    • All Webcasts & Series
    • Devices
      • Stratix IV (E, GX, GT)
      • Stratix III (L and E)
      • Stratix II GX
      • Stratix II
      • Stratix
      • Arria II GX
      • Arria GX
      • Cyclone IV (E and GX)
      • Cyclone III (and LS)
      • Cyclone II
      • MAX II
      • HardCopy IV (E and GX)
      • HardCopy III
      • HardCopy II
    • Design Software
      • Quartus II
      • SOPC Builder
    • Intellectual Property
      • Embedded Processor
      • DSP
    • Technology
      • DSP
      • Memory
      • Embedded Processor
      • High-Speed Serial I/O
      • Signal Integrity
    • End Market
      • Automotive
      • Communications
      • Consumer
      • Industrial
      • Military
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates