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Available Now, On-Demand |
Overview
With today’s requirements for high-speed memory interfaces surpassing 1 Gbps, FPGA silicon and IP must be designed to provide robust signal integrity and address the challenges of implementing DDR3 interfaces. Simulation still plays an important role in validating signal levels and timing margins.
This webcast will discuss the challenges of implementing DDR3, and available solutions.
At this webcast, you’ll learn :
- The JEDEC requirements for DDR3
- How to address read/write leveling in your system
- How to reduce power consumption on your board and track PVT
Who Should View
- System architects
- Hardware and system design engineers
- FPGA developers
- Signal integrity engineers
Presenters
Salman Jiva
Sr. Product Marketing Engineer, Altera Corporation
As senior product marketing engineer for Altera’s high-end FPGA product lines, Salman Jiva is responsible for the technical analysis and marketing of the signal integrity and high-speed interfaces for Altera FPGAs. Prior to joining Altera, he spent six years at Cisco Systems as an ASIC signal integrity engineer for their enterprise line of switches. Mr. Jiva holds an MS in Electrical Engineering from Santa Clara University with a concentration in communication systems.
Todd Westerhoff
VP Software Products, SiSoft
Todd Westerhoff, vice president of software products for SiSoft, has over 26 years experience in the modeling and analysis of electronic systems, including 10 years of signal integrity experience. Prior to joining SiSoft, Mr. Westerhoff managed a high-speed design group that provided static timing, signal integrity and design rule consultation to various ASIC and system engineering groups within Cisco Systems, Inc. Mr. Westerhoff joined Cisco through Hammerhead Networks, where he was a high-speed design specialist. Prior to Hammerhead, he was the SPECCTRAQuest Product Manager for Cadence Design Systems. Before joining Cadence, he was a signal integrity consultant to a number of Fortune 500 companies. Mr. Westerhoff has also held product marketing positions at Compact Software, Racal-Redac, FutureNet and HHB-Systems. Mr. Westerhoff holds a B.E. degree in electrical engineering from the Stevens Institute of Technology in Hoboken, New Jersey.
