Dynamically Reconfigure Transceivers for Multiple Data Rates and Protocols in FPGAs
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Available Now, On-Demand!
Featured Technology: Stratix® II GX FPGAs
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Overview
The rapid adoption of high-speed serial interconnect in recent years has posed new challenges to engineers. The data rates of serial protocol and proprietary protocol standards are doubling and quadrupling to keep up with the ever increasing bandwidth requirements of today’s applications. At the same time, new serial protocol standards are ratified to address new market requirements.
Designers are faced with the challenge of designing systems that support the newer and faster serial protocols while continuing to support slower legacy versions. Until now, design engineers had to design with multiple ASSPs and boards to support different data rates and protocols.
Dynamic reconfiguration delivers an elegant solution to this challenge. With dynamic reconfiguration, Stratix II GX FPGAs with embedded transceivers are the Swiss Army Knife of high-speed serial protocols.
In this webcast, you will learn:
- About high-speed connectivity trends
- How to support multiple rates and protocols on FPGAs with embedded transceivers
- How dynamic reconfiguration can increase productivity for you and your customers
Who Should View
- System architects
- Hardware and system design engineers and managers
- FPGA developers
- Signal integrity engineers
Presenters
Joel Martinez
Senior Product Marketing Manager, Altera Corporation
Joel Martinez is a senior product marketing manager in Altera’s high-end FPGA group, responsible for FPGAs with embedded high-speed transceivers. Joel joined Altera in 2002 and has more than 19 years of semiconductor experience. Joel held engineering and marketing positions at Agere Systems, Hitachi Semiconductor, Sony Semiconductor, TriQuint, and National Semiconductor. He holds a BSEE from San Francisco State University.
Sridhar Krishnamurthy
Senior Applications Engineer, Altera Corporation
Sridhar Krishnamurthy has been working with Altera since 2005 in the high-speed applications group. Prior to joining Altera, Sridhar designed systems for Fibre Channel, SATA, and SAS protocols. He holds a Masters degree in electrical engineering from University of Texas at Dallas and a BS in electronics and communications engineering from University of Madras, India.
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