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Available Now On-Demand! |
Overview
Today’s systems demand more performance, higher integration, and customization capabilities, but most systems cannot afford an increase in power budget. Learn how Altera developed a high-end 65-nm FPGA that met system designers' needs to increase performance and logic capacity, while reducing power. You'll learn to use Altera's unique technologies that help reduce power consumption in your designs.
This 60-minute net seminar includes an in-depth look at:
- Programmable Power Technology
- Selectable core voltage
- Power-optimized memory interfaces
- Quartus® II software PowerPlay power optimization
Who Should View
- FPGA and ASIC developers
- Engineering and technical managers
- System architects
Drawing
All participants who attend this net seminar between April 25, 2007 and June 15, 2007, and complete the post-presentation survey, will be entered into the drawing for a chance to win a Toshiba 30GB Gigabeat Portable Music Player (US$350).
Presenters
Vaughn Betz
Director, Software Engineering
Vaughn Betz is a Director of Engineering at Altera. He is one of the architects of the Stratix® and Cyclone® FPGA families, the Quartus II placement and routing engine, and the Quartus II power analysis and optimization features. Dr. Betz authored the book Architecture and CAD for Deep-Submicron FPGAs and numerous technical papers. He has over thirty issued and pending patents.
Prior to joining Altera, Dr. Betz was a co-founder and Vice President of Engineering at Right Track CAD. He holds a Bachelor of Sciences degree from The University of Manitoba, a Master of Sciences degree from The University of Illinois, and a PhD from the University of Toronto, all of which are in electrical engineering. The Versatile Place and Route CAD system he developed for his PhD thesis remains the most widely used academic placement, routing, and architecture exploration system for FPGAs.
Sanjay Rajput
Product Marketing Manager, Stratix Series FPGAs
As product marketing manager, Mr. Rajput is responsible for marketing the industry-leading Stratix III FPGA family. Since 2001, his marketing responsibilities have spanned across many Altera products including Stratix, Stratix GX, Stratix II, HardCopy®, MercuryTM, and APEX® devices. Prior to his product marketing roles, Mr. Rajput was responsible for Altera’s strategic marketing and promotion for the networking market segment. In addition to his marketing responsibilities at Altera, he has a strong technical background in FPGAs, power consumption, and transceivers. When Mr. Rajput joined Altera as an applications engineer in 1999, he brought design experience in embedded systems, aerospace power systems, and security access and intrusion systems. Mr. Rajput earned his bachelors degree in computer engineering from the University of Toronto.
