Meet Your FPGA Design Requirements with Maximum Productivity
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Available Now On-Demand!
August 27, 2007 - August 27, 2008
Featured Technology: Stratix® III FPGAs
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Overview
Not having an optimal CAD tool that automatically exploits every feature available in high-end devices results in decreased performance and increased power consumption in FPGAs. As a result, design engineers spend a lot of effort trying to close timing and meet power budgets, which in turn results in decreased productivity for the engineer.
An optimal solution for any designer is to have an FPGA with a CAD tool that provides the fastest time-to-market while automatically utilizing every feature available in the FPGA. Stratix III FPGAs and Quartus® II software, when compared to the Virtex-5 and ISE CAD tool, provide:
- A 25% performance boost (a two speed grade advantage) with no degradation in performance as Stratix III FPGAs fill up
- 50% faster compile times with ½ the peak memory
- 45% less power
- A risk-free path to structured ASICs—HardCopy® devices
After viewing this net seminar you will know how:
- Stratix III FPGAs and Quartus II software automatically deliver the highest performance and the lowest power
- Stratix III FPGAs and Quartus II software maximize your productivity while enabling the fastest time-to-market
- Quartus II software's incremental compile, multi-threaded support, chip planner, SOPC builder, and push-button synthesis technology make it the ideal CAD tool for your next generation high density, high performance designs
- Quartus II software is extremely stable compared to the nearest competitor's CAD tool
Who Should View
- System architects
- Embedded system design engineers
- FPGA and ASIC developers
- Engineering and technical managers
Drawing
All participants who attend this net seminar between August 27, 2007 and October 1, 2007 and complete the post-presentation survey will be entered into the drawing for a chance to win an RCA Lyra 20-GB Audio/Video Jukebox (US$160 value)!
Official Rules
Presenter
Paul McHardy
Supervising Member of Technical Staff,
Software and Systems Engineering, Altera Corporation
Paul McHardy leads a team of engineers responsible for analyzing the performance and quality of Altera FPGA architectures and Quartus II design software. This work is used to guide future product development as well as to provide scientific data for public benchmarking results. Since joining Altera in 2001, Mr. McHardy has also worked as an engineer on the Physical Synthesis algorithm development team. Prior to joining Altera, Mr. McHardy was employed by a digital design contracting firm. Mr. McHardy holds an M.A.Sc degree in computer engineering from the University of Toronto and a B.A.Sc from Queen’s University.
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