Minimize SSN and Jitter with Advanced Transceiver Technology
Available Now, On-Demand
Length: 30 minutes
As data rates and the number of transceiver channels in advanced FPGAs increase, it’s increasingly important that the FPGA is designed to properly isolate analog and digital sources. This webcast presents available architectural advantages, and describes how those advantages minimize the effects of simultaneous switching noise (SSN) and jitter.
View this webcast to learn:
- The basics of SSN and jitter
- The relationship between SSN and jitter, and how one affects the other
- How advanced transceiver architectures can minimize SSN and jitter
Presenter: Dr. Mike Peng Li
Principal Architect and Distinguished Engineer, Altera Corporation
This webcast will be available until May 18, 2009.
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