Available Now, On-Demand
Length: 40 minutes
When selecting an FPGA for its transceiver capabilities, it is important to understand the underlying serializer/deserializer (SERDES) architecture and how it enables you to design a robust serial link. This webcast discusses the transceiver architecture and clocking in 40-nm Stratix® IV GX FPGAs and HardCopy® IV GX ASICs. The webcast focuses on clock generation and recovery, advanced oscillators, power integrity, and equalization.
View this webcast to learn about:
- Transceiver architecture
- Clock recovery and jitter tracking
- Random jitter reduction with advanced oscillators
- Transceiver equalization and signal impairment correction
- Analog power and power integrity
Presenter:
Dr. Mike Peng Li, Principal Architect
