Build up to 96-Port SGMII GigE With Stratix III FPGAs

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• Download the SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices application note
  
  
• Get more information on SGMII

Stratix III FPGAs support SGMII GigE operation on LVDS I/O pins at 1.25 Gbps. With Stratix III FPGAs, you can build communications systems requiring single or multiple (up to 96) Ethernet links quickly and simply while meeting jitter and tolerance requirements. SGMII GigE operation is:

• Available on fast, mid-range, and industrial speed grade devices
• Meets jitter and tolerance requirements with LVDS pins