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Automotive Software-Defined Radio Systems Using FPGAs

Software-defined radio (SDR) refers to wireless communication in which the transmitter modulation and the receiver demodulation are both generated through software. An SDR receiver has an analog-to-digital (A/D) converter right after the antenna or with one interface unit in between. Mixing and baseband processing are done digitally and are controlled by software. The main advantage of this approach is flexibility, as the software runs on one common hardware platform for any type of receiver configuration. You can then extract a common set of functions needed in hardware to address all possible receivers and reconfigure the hardware when a new receiver is needed.

Figure 1 shows a typical automotive SDR system. An SDR receiver consists of a channel-processing module and a decoder module. The channel-processing module does channel selection, filtering, and equalizing by using digital downconverters, cascaded integrated comb (CIC) filters, and finite impulse response (FIR) filters. Several receiver configurations can require a different set of channel processing modules, which then can be reloaded into Altera's Cyclone® series FPGAs under the control of the SDR controller. A waveform module then processes the decoded audio signals.

Figure 1. Automotive SDR

Figure 1. Automotive Software Defined Radio

Note:

  1. UART = universal asynchronous receiver/transmitter

Altera provides various intellectual property (IP) cores, such as numerically controlled oscillator (NCO), FIR, infinite impulse response (IIR), fast Fourier transform (FFT), and constellation mappers that can be used to implement the channel processing, decoding, and waveform modules. You can also implement IP cores such as control area network (CAN), USB controllers, and the 32-bit Nios® II RISC embedded soft core processor in Cyclone series FPGAs to implement the SDR control modules.

Cyclone series FPGAs and solutions provide you with unparalleled flexibility and capability at pricing competitive with ASICs.

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