A navigation system is one of the key applications within the automotive space that utilizes a fair amount of graphics processing. The graphics processing complexity varies from a simple turn-by-turn (TBT) navigation to a more sophisticated 3D navigation system. Figure 1 shows a typical block diagram of a navigation system. The architecture consists of a host CPU (which is generally a Hitachi SH4, Motorola Power PC, or a TI OMAP processor) with a graphics processor. Various peripherals talk to these processors, including keyboards and thin-film transistor (TFT) displays.
Figure 1. Typical Automotive Navigation System
Graphics processing requires the computation of numerous algorithms such as scaling, filtering, and alpha blending. Unlike digital signal processors or ASSPs, FPGAs are better suited to perform these computationally-intensive algorithms because they can handle multiple instructions in a single clock cycle.
Figure 2 shows a low-cost graphics implementation. The video-in can be a BT.656 input (YUV 4:2:2), with color space converter (CSC) to output RGB. The memory interface to the Avalon® system interconnect fabric accommodates high graphic computations. Memory types that are supported include: SDR, DDR, and DDRII. The Altera Nios® II 32-bit embedded processor is primarily used for graphics processing (line draw, frame creation) and provides additional control functions. Graphics hardware acceleration can include functions such as BitBlt (copy object into frame buffer, 2D-DMA transfer, possibly with blending). Alpha blending can have multiple channels. The Cyclone® FPGA series is capable of supporting LVDS graphics output for remote display applications.
Figure 2. Low-Cost Graphics Implementation of Automotive Navigation System
Notes:
- DMA = direct memory access
- FIFO = first-in first-out
With efficient device architecture for graphics processing, the Cyclone FPGA series meets the performance and price-level requirements of cost-sensitive routing applications. Complementing this powerful combination is Altera's Nios II embedded processor.
Related Links
- Digital Signal Processing (DSP) in FPGAs
- DSP for Graphics Processing
- Other Automotive Reference Designs
- Automotive Grade Devices
- Nios II 32-bit Embedded Processor
- IP MegaStore™
- Altera’s Flexible Graphics Controller Reference Design
- Platform ASSP Replacement Infotainment System (PARIS) Development Platform
