DTV Video Decoder
Service providers use digital television (DTV) video decoders to decompress digital video and audio to make changes to the video program (such as adding local advertisements or other programming). Decoders often receive data as a single-program transport stream (SPTS), transmitted via the digital video broadcasting (DVB) asynchronous serial interface (ASI). The SPTS includes audio, video, and ancillary data inputs that are encoded with compression schemes such as that of the Moving Picture Experts Group (MPEG)-2. The decoder separates the audio, video, and ancillary data into separate streams and decodes (or decompresses) the audio and video data.
DTV video decoders can support the standard definition (SD) or high definition (HD) digital video format. The decoder receives the SPTS at the DVB-ASI speed of 270 Mbps from other networked video delivery equipment. After it decodes the data, the DTV video decoder provides a video program in the video serial digital interface (SDI) format at SD speed of 270 Mbps or the HD speed of 1.485 Gbps. Figure 1 shows a typical Altera® programmable logic solution for a DTV decoder.
Figure 1. Altera Usage Example for DTV Video Decoders
Altera solutions include proven reference designs and intellectual property (IP) cores from partners for implementing video decoders for DTV video applications. On the receiving side of the decoder, Altera offers the ASI MegaCore® function, which provides a serial interface for MPEG-2 TS. After uncompressing and editing, the video can either be sent out in an uncompressed format by using the SDI or in a compressed format by using the ASI. Multiple customers have successfully implemented the ASI and SDI MegaCore functions in their end systems using Cyclone®, Cyclone II, Stratix®, Stratix II, and Stratix GX device families. The Altera Video and Image Processing Library Suite provides access to a number of video processing functions to video designers implementing the DTV video decoder blocks.
Feature-Rich Programmable Solutions for DTV Video Decoders
The feature-rich architecture of the Stratix II (with HardCopy® structured ASIC versions available) and the low-cost Cyclone III device families provides excellent solutions for implementing video decoders. These programmable device families provide flexibility, performance, integration, and design resources that are not available in any other solution.
Stratix II devices use a high-performance architecture that accelerates block-based designs for maximum system performance. Stratix II devices include high-performance digital signal processing (DSP) blocks to implement DSP functions such as discrete cosine transform (DCT), up to 9 Mbits of embedded TriMatrix memory, up to 180K equivalent logic elements (LEs), and flexible I/O standard support. The Stratix II series feature set provides an ideal solution for implementing video pre-processing functions and video compression.
Altera’s low-cost Cyclone III FPGAs are built on a 65-nm, low-power process technology. The Cyclone III family is composed of 8 devices ranging from 5K to 120K logic elements (LEs) and up to 534 user I/O pins. Cyclone III FPGAs offer up to 4 Mbits of embedded memory, 288 embedded 18 x 18 multipliers, and dedicated external memory interface circuitry making them ideal for implementing applications such as modulators in digital broadcasting applications.
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