The Altera® Motor Control Development Framework lets you easily create integrated, high-performance drive-on-a-chip motor control designs for Altera Cyclone® FPGAs and SoCs. The framework comprises reference designs, software libraries, intellectual property (IP) cores, and a portfolio of motor control hardware platforms supporting the development of motor control systems in a single FPGA.
Figure 1: Motor Control Development Framework
The Motor Control Development Framework seamlessly integrates system-level design and software development tools for embedded Nios® II and ARM® processors, allowing you to extend and customize the motor control reference designs to meet your own application needs. Our Cyclone FPGAs, with high-performance fixed- and floating-point DSP functionality and Nios II soft processor support, offer a scalable and flexible platform for integration of cost-effective single- and multiaxis drives on a single FPGA.
Motor Control Reference Designs
Altera provides a suite of single-and multi-axis drive-on-a-chip reference designs that include a complete FOC IP subsystem integrated with key motor control and interface IP, and system software running on the integrated processor.
Motor Control Development Kits
Motor control development kits include:
- A multiaxis motor control system connecting Altera’s Cyclone V SoC Development Kit to the quad-axis multiaxis motor control power board. Altera’s Cyclone V E Development Kit and Terasic’s DE-2115 board are also supported FPGA platforms
- A single axis motor control system that connects the above FPGA development boards to the single axis power board and motor on the devboards.de HSMC-FalconEye board
- The FalconEye-Hunter motor control platforms from EBV Elektronik
Optimized Motor Control Design Flow
Optimizing motor control algorithms and designs requires versatile tools and a practical tool flow. Figure 2 shows how the right tool flow helps model and simulate the system, implement complex algorithms with low latency, integrate the system, and fine-tune the performance to the exact needs of the motor drive.
Figure 2. Optimize Drive Designs with an Integrated, Flexible Design Flow
You can get powerful and easy-to-use development tools, such as Quartus® II design software, and system integration tools, such as Qsys and DSP Builder for DSP optimization. With support for model-based environments such as MATLAB/Simulink to model the algorithm, you can build a motor control system that can be directly and optimally mapped to a HDL implementation by DSP Builder for optimized Altera-based drive designs. You can develop your software using industry-standard software tools and integrated with FPGA DSP and interface IP using the Qsys tool.
The framework supports optimal partitioning decisions between software running on an integrated processor and IP performing portions of the motor control algorithm in the FPGA. For example depending on the performance requirements of your system or the number of axes you need to support, you can implement position, speed, and current control loops entirely in software or accelerate DSP-intensive functions such as the FOC current control loop in the FPGA for ultra-low latency. The development framework gives you the ability to scale performance via processor offload to the FPGA, helping you meet the most demanding requirements.
Flexible SoC Design Entry Methodologies
Use Simulink and Embedded Coder from MathWorks to generate C/C++ code for Altera Cyclone V SoCs. When used in combination with Altera SoC support from HDL Coder, this solution can be utilized in a hardware/software workflow spanning simulation, prototyping, verification, and implementation on Altera SoCs. For more information, visit www.mathworks.com/altera-soc.
- Drive-on-a-chip Reference Design application note (PDF)
- Motor Control IP Suite data sheet (PDF)
- Multiaxis Motor Control Board reference manual (PDF)
- White paper: Advantages of Using FPGAs in Precision Inverter Modules (PDF)
- SoC overview
- Cyclone V SoCs
- Motor drive on a single SoC
- Embedded processors for Altera FPGAs