Radar, secure communications, and electronic warfare all have at their roots in high-performance digital signal processing (DSP) chains with a performance range from one GFLOPS to ten TFLOPS. Achieving this level of performance, while still maintaining reasonable size, weight, and power (SWaP), is a challenge.
System architects often develop their concepts and models in MathWorks's MATLAB, then a separate team quantizes the mathematical models for execution in fixed-point-capable hardware. This quantization step often introduces deviation from original model and suffers from possible dynamic range constraints or other system issues.
Modern FPGAs offer a highly efficient GFLOPS/Watt ratio to help maintain SWaP. An IEEE 754- compliant floating-point processing chain can significantly reduce the processing burden. Reducing the need for repeated normalization thus increases the hardware efficiency. The floating-point capability of FPGAs can eliminate the quantization step between MATLAB and hardware implementation while maintaining the designer's original system specification.
Figure 1 highlight some of the high-performance DSP capabilities in Stratix® V FPGAs. These include integrated coefficient registers, hard pre-adders, and three multiplier modes for flexibility. The DSP architecture along with DSP Builder Advanced Blockset with fused data-path flow saves memory and routing resources while enabling designers to choose the precise blend of precision, utilization, and power.
Figure 1. 18-bit and High-Precision Modes
Mouseover highlights in image to enlarge
Altera offers solutions, reference designs, and technical support to address military DSP applications. For more details, please contact us at email@example.com.
|28-nm Variable-Precision DSP Block Architecture||Learn how the DSP block architecture optimizes floating-point precision in each block to an 18-bit or high-precision mode.|
|DSP Builder Advanced Blockset
(includes fused-datapath flow)
|Read about the DSP Builder blockset and how it utilizes a fused-datapath flow to shorten development time and improve code efficiency.|
|Floating Point Megafunctions||Explore how floating-point megafunctions allow parametric tuning of GFLOP performance, power, and area.|
|White Paper: Achieving One TeraFLOPS with 28-nm FPGAs (PDF)||Achieve 1 teraFLOP FPGA performance in a single FPGA by maximizing fixed- and floating-point performance.|
|White Paper: An Independent Analysis of Altera's FPGA Floating-point DSP Design Flow (PDF)||This BTDI study validates and benchmarks Altera's floating-point DSP tool performance and its ease of use.|
|"Floating-Point FPGAs for DSP Bring High Precision to Radar and EW Systems"||Use floating-point DSP in FPGAs to achieve high precision and dynamic range while reducing power and latency.|
|"Signal processing approaches for electronic warfare and signals intelligence spark debate"||This comparison of FPGA, GPU, and DSPs in high-performance military designs shows how to use COTs boards to shrink development times.|
|White Paper: Using Floating-Point FPGAs in DSP for Radar (PDF)||Learn about the power, performance, and dynamic range advantages of FPGAs in radar applications.|
|White Paper: JESD204A for wireless base station and radar systems (PDF)||Use the JEDEC JESD204A data converter interface with Altera's Stratix V FPGAs and NXP ADCs for synthetic beamforming and steering in radar and radio systems.|
|Floating-Point DSP Solutions||Use MathWorks's MATLAB and Simulink to solve floating-point challenges in developing radar applications.|
|IEEE Lecture: "Digital Signal Processing for Radar Applications," March 2011||Learn how to optimize the modeling and implementation of STAP back-end processing in an FPGA.|
|White Paper: Accelerating DSP Designs with the Total 28-nm DSP Portfolio (PDF)||Use DSP tools and resources to tailor designs to different applications based on the desired performance and precision.|
Optimize variable-precision DSP in Arria® and Cyclone® series FPGAs with this overview of DSP resources and tools.
View the MegaCore® functions available for next-generation electro-optical and infrared systems in Cyclone FPGAs.
|Learn about industry -leading and proven transceivers for 28-Gbps FPGAs.|
|White Paper: Boosting System Performance with External Memory Solutions (PDF)||Explore external memory solutions including Altera’s PHY offerings and new memory controller.|