Solving SWaP Constraints in Military Applications
 In today's military platforms, reducing system size, weight, and power (SWaP) is critical for operational life and budgetary constraints. SWaP budgets are driven down to extend mission life, reduce form factor for better mobility and logistics, and expand the market. In platforms such as radar, SWaP constraints are different because there is a need to support larger arrays for beam flexibility, increased range, and faster steering while still staying within the budget. Altera® FPGAs continue to provide more flexibility and functionality at reduced costs by enabling new SWaP systems with smaller footprints, lighter weight, and smaller batteries. Whether your military platform requires a low-cost, low-power Cyclone® III FPGA or a high-performance, high-density Stratix® III FPGA, Altera has the SWaP-based production implementations.
Altera FPGA Solutions
Cyclone III FPGAs are optimized for SWaP production. The combination of resource capacity (logic elements, embedded memory, multipliers, and I/O), coupled with the most aggressive power reduction techniques and smallest packaging, enable superior SWaP implementations. Low-power Cyclone III FPGAs are optimized for battery-operated radios with sufficient signal processing resources for advanced waveforms.
Stratix IV FPGAs provide maximum functionality using minimum power with advanced architecture capabilities, including programmable power technology and voltage scaling. With the maximum digital signal processing (DSP) performance available, these FPGAs are designed to address the broadest range of airborne and ground mobile radios (e.g., AMF, GMR, manpacks, and special operation modems), as well as high-performance radar and missile systems.
Secure Communications
Military software defined radios (SDRs) are now entering their production phases after years of feasibility, development, and demonstration implementations. Advanced waveforms for SDRs require flexibility and functionality beyond low-power DSP devices. New SDR designs require programmable FPGA capabilities for advanced waveforms (processing intermediate frequency (IF), modulation, and bit-level functions at megabits per second), triple-play packet processing, and military software communications architecture (SCA) middleware (for hardware independence). Ultimately, the power consumption of the SDR electronics adversely affects mission life in battery-operated devices or may surpass equipment cooling requirements in extreme environments.
SWaP design challenges for battery-operated SDRs:
- Severe size and weight restrictions: The smallest implementations are less than 10 inches.
- Power consumption directly affects mission life: Using typical military batteries, today's programmable electronics consume over 4 watts, and only yield a 6-hour mission life for the overall radio system.
- Power budgets dominated by digital electronic processing: As waveform bandwidth and complexity increases, digital processing absorbs more functionality and power within the radio.
- Digital logic implementation trade-offs: Choices for digital processing vary from CPU to ASIC. Typically, DSP devices and FPGAs provide the best combination of functionality and flexibility, while encountering power trade-offs.
- Static versus dynamic power trade-offs: Due to the duty cycle of radio modes, standby operation typically dominates radio use by a factor of 10:1. It is therefore imperative to minimize leakage power of digital electronics during standby operation.
- Voltage and frequency scaling trade-offs to save power: With careful system design, both voltage and frequency can be scaled back during standby states, leaving only a small portion of the radio functional.
- Software and hardware partitioning for power: Software designers need to leverage radio operational modes and intelligently manage hardware resources to effectively minimize power use.
Previous attempts to meet SDR requirements for production units have fallen short. Waveform requirements—such as variations of the soldier radio waveform (SRW), highband networking waveform (HNW), tactical targeting network technology (TTNT), and mobile user objective system (MUOS) waveform—are too power sensitive for high-performance FPGAs, but beyond the capabilities of low-power DSP devices and low-cost FPGAs. As data rates move from Kbps to Mbps, low-power DSP devices no longer have the functionality for IF, modulation, and bit-level processing. Some low-cost FPGAs need multiple devices to implement the required functionality and thus limit integration capability for reducing size and weight.
Suppliers of high-performance FPGAs have tried to exploit features like voltage scaling and partial reconfiguration (for waveform integration) with little success, often causing delays in development and adding increased system risk. Without careful control of device design and manufacturing constraints, voltage scaling (lowering the voltage during radio standby conditions to reduce FPGA leakage power) can degrade verification and susceptibility of functional, timing, and I/O parameters. Partial reconfiguration (the ability to reprogram portions of the FPGA while other functionality continues) for power reduction is ineffective in high-performance, high-power process FPGAs—the unused functional areas can draw more than a watt of leakage (static) power during radio standby operation, a significant portion of time (remember the 10:1 standby to operating ratio).
Radar
Active Electronically Scanned Arrays (AESAs) are a powerful technology for creating highly adaptive steerable beams able to track multiple targets. To take full advantage of a system’s steering capabilities, as much signal processing capability as possible must be moved into the forward radiating elements of the system. This may include waveform creation and compression, beam forming, correlation, and pre-processing. As more of these functions are performed in optimized, parallel FPGA logic, beam-forming algorithms and waveform adaptivity can be accelerated, increasing reaction times in the system.
Stratix series FPGAs are the right tool for optimizing radar system performance. High logic density allows more functions in a single device. Increased DSP elements streamline matrix mathematical functions and increase flexibility. Flexible 18 x 18-bit multipliers can be split into 9 x 9 elements or combined into power-and-logic efficient 54 x 54-bit multipliers for floating-point operations. High-speed transceivers allow fast telemetry streaming on a variety of serial digital interface standards (PCI Express, FPDP, Gigabit Ethernet, etc.)
Stratix series FPGAs offer a wide variety of technology solutions for adaptive weight calculation and adaptive beam forming in sensor systems.
- Design balance between performance and power (radar systems have severe constraints in size, power, and in latency and speed performance)
- Large numbers of streaming serial I/O pins (requirement for higher resolution analog-to-digital converters and sensors)
- High resistance to temperature extremes to prevent logic and clock drift
- Simple replacement and upgrade capability for extended mission life
Advances in Programmable Power Technology, selectable core voltage, and PowerPlay power optimization technology allow you to calculate and manage trade-offs between power and performance. These design features are important when power budgets or design envelopes change in system design, or when overall performance requirements change to require increased bandwidth and reduced latency in processing elements.
Advanced sensor systems are also seeing a convergence in missions to include electronic warfare, reconnaissance and mapping, and even ad hoc communications. Larger and more capable FPGAs are required to accommodate these new missions and waveforms, and design tools must keep up. Equally important as primary architecture design support is the ability to add complex new logic blocks that can be seamlessly integrated into a design.
|
 |
|
Literature
> 
