In today's military platforms, reducing system size, weight, and power (SWaP) is critical for operational life and budgetary constraints. SWaP budgets are driven down to extend mission life, reduce form factor for better mobility and logistics, and expand the market.
Altera® FPGAs continue to provide more flexibility and functionality at reduced costs by enabling new SWaP systems with smaller footprints, lighter weight, and smaller batteries. Whether your military platform requires a low-cost, low-power Cyclone FPGA or a high-performance, high-density Stratix FPGA, Altera has the SWaP-based production implementations.
Secure Communications
Military software defined radios (SDRs)require programmable FPGA capabilities for advanced waveforms (processing intermediate frequency (IF), modulation, and bit-level functions at megabits per second), and triple-play packet processing.
SWaP design challenges for battery-operated SDRs:
- Severe size and weight restrictions: The smallest implementations are less than 10 inches
- Power consumption directly affects mission life: Using typical military batteries, today's programmable electronics consume over 4 watts, and only yield a 6-hour mission life
- Power budgets dominated by digital electronic processing: As waveform bandwidth and complexity increases, digital processing absorbs more functionality and power
- Digital logic implementation trade-offs: DSP devices and FPGAs provide the best combination of functionality and flexibility
- Static versus dynamic power trade-offs: Due to the duty cycle of radio modes, standby operation typically dominates radio use by a factor of 10:1. Leakage power must be minimized during standby operation
- Voltage and frequency can be scaled back during standby states, leaving only a small portion of the radio functional
Software and hardware partitioning for power can manage hardware resources to effectively minimize power useSWaP design challenges for battery-operated SDRs:
- Severe size and weight restrictions: The smallest implementations are less than 10 inches.
- Power consumption directly affects mission life: Using typical military batteries, today's programmable electronics consume over 4 watts, and only yield a 6-hour mission life for the overall radio system.
- Power budgets dominated by digital electronic processing: As waveform bandwidth and complexity increases, digital processing absorbs more functionality and power within the radio.
- Digital logic implementation trade-offs: Choices for digital processing vary from CPU to ASIC. Typically, DSP devices and FPGAs provide the best combination of functionality and flexibility, while encountering power trade-offs.
- Static versus dynamic power trade-offs: Due to the duty cycle of radio modes, standby operation typically dominates radio use by a factor of 10:1. It is therefore imperative to minimize leakage power of digital electronics during standby operation.
- Voltage and frequency scaling trade-offs to save power: With careful system design, both voltage and frequency can be scaled back during standby states, leaving only a small portion of the radio functional.
- Software and hardware partitioning for power: Software designers need to leverage radio operational modes and intelligently manage hardware resources to effectively minimize power use.
Radar
Active Electronically Scanned Arrays (AESAs) are a powerful technology for creating highly adaptive steerable beams able to track multiple targets. To take full advantage of a system’s steering capabilities, as much signal processing capability as possible must be moved into the forward radiating elements of the system. This may include waveform creation and compression, beam forming, correlation, and pre-processing. As more of these functions are performed in optimized, parallel FPGA logic, beam-forming algorithms and waveform adaptivity can be accelerated, increasing reaction times in the system.
Stratix series FPGAs are the right tool for optimizing radar system performance. High logic density allows more functions in a single device. Increased DSP elements streamline matrix mathematical functions and increase flexibility. Flexible 18 x 18-bit multipliers can be split into 9 x 9 elements or combined into power-and-logic efficient 54 x 54-bit multipliers for floating-point operations. High-speed transceivers allow fast telemetry streaming on a variety of serial digital interface standards (PCI Express, FPDP, Gigabit Ethernet, etc.)
Stratix series FPGAs offer a wide variety of technology solutions for adaptive weight calculation and adaptive beam forming in sensor systems.
- Design balance between performance and power (radar systems have severe constraints in size, power, and in latency and speed performance)
- Large numbers of streaming serial I/O pins (requirement for higher resolution analog-to-digital converters and sensors)
- High resistance to temperature extremes to prevent logic and clock drift
- Simple replacement and upgrade capability for extended mission life
Advances in Programmable Power Technology, selectable core voltage, and PowerPlay power optimization technology allow you to calculate and manage trade-offs between power and performance. These design features are important when power budgets or design envelopes change in system design, or when overall performance requirements change to require increased bandwidth and reduced latency in processing elements
