Large automated test equipment (ATE) and communication test systems have used chassis implementations that:
- Provide equipment options to integrated device manufacturers and integrated test houses, with flexibility, scalability, and longevity for the widest variety of devices under test (DUTs).
- Accelerate complex hardware and software development across multiple platforms, teams, and locations.
- Easily upgrade functionality for emerging protocols.
ATE requires many instrument cards to provide the functionality and extreme pin density needed to simultaneously test multiple memory devices or to test complex system-on-chip (SOC) DUTs. Communication testers use multiple line interface cards to generate and analyze traffic for evaluating large routers and switches. These subsystems must:
- Accommodate multiple cards for pin electronics, formatting, sequencing, and timing analysis.
- Provide backplane structures with special timing, control, and data transfer capabilities (historically proprietary).
Now you can implement chassis backplane architectures (see Figure 1) using standardized serial implementations with integrated gigabit transceivers (e.g., PCI Express (PCIe), LXI, and IEEE1588) on Stratix® V FPGAs, that allow:
- Significantly increased subsystem data transfer rates and advanced timing capabilities.
- Lower development costs and a smaller equipment footprint.
- Higher pin densities per FPGA component, while lowering platform power requirements.
Our Stratix V FPGAs introduce family members with 10GBASE-KR backplane support.
Figure 1. Chassis-Based Architectures