Reduce Design Costs
In addition to delivering industry-leading, high-quality products that assist in reducing overall costs, Altera helps reduce costs through its HardCopy® ASIC and process migrations.
HardCopy ASICs
HardCopy ASICs are a risk-free, cost-reduction path available to only Altera® FPGA customers. You can simply use Altera FPGAs as your prototype vehicle, provide Altera your register transfer level (RTL) design when available, and receive fully functional silicon in roughly 18 weeks.
With a 65 to 85 percent die size reduction, HardCopy ASIC usage can result in significant cost reductions. In addition to significant cost reduction, HardCopy ASICs enable up to 50 percent performance improvement and 70 percent lower core power than the prototype FPGA. HardCopy ASICs are pin-to-pin compatible with the prototype FPGA and trigger no PCB respins.
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