Digital Predistortion
Market pressures demand that today’s mobile base transceiver stations (BTSs) be more cost effective than ever before. To reduce BTS costs, designers are building more-efficient, less-expensive power amplifier (PA) architectures by employing digital predistortion (DPD) techniques. Altera's digital predistortion reference design demonstrates the suitability of Stratix® series FPGAs to implement digital predistortion solutions.
Power Amplifiers in 3G Base Transceiver Stations
As a key part of mobile BTSs, PAs are responsible for amplifying weak signals without adding distortion. High-performance PAs are expensive to build and typically account for 30 to 35 percent of the cost of a mobile BTS. Two factors have significant impact on the way next-generation PAs are being designed:
- Demand for less costly BTSs: At one-third the cost of BTSs, the high costs of today’s PAs are leading designers to develop power amplifier architectures that are less expensive.
- Higher efficiency and linearity of PAs: The 3G standards and their high-speed mobile data versions employ non-constant envelope modulation techniques. As a result, PA designers must achieve high efficiency and linearity over a large amplitude range. This is necessary to maintain high adjacent channel leakage ratio (ACLR) and low error vector magnitude (EVM).
Improved Efficiency and Linearity at Reduced Costs
Class A power amplifiers meet the stringent linearity requirements of the 3G standards. However, they are designed with expensive high-power transistors and are inefficient in converting DC power to radio frequency (RF) power. An attractive alternative for OEMs is to use power-efficient, less-expensive, nonlinear Class AB, B, and C power amplifiers. To compensate for the amplifiers’ nonlinearity, different linearization techniques are employed (shown in Table 1). Although the feed-forward technique is commonly used today, DPD is better suited for 3G systems since it offers higher efficiency and greater flexibility at a lower cost.
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Table 1. Linearization Techniques
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Technique
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Correction (1)
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Bandwidth (2)
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Efficiency
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Flexibility (3)
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Cost
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In-line Predistortion
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2 to 3 dB
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15 to 25 MHz
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5 to 8%
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Low
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Very Low
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Analog Predistortion
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3 to 5 dB
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15 to 25 MHz
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5 to 8%
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Low
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Low
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Cross-Cancellation
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15 to 20 dB
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10 to 20 MHz
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10 to 12%
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Medium
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Medium
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Feed-Forward
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30 dB
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25 to 60 MHz
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6 to 10%
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Medium
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High
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Digital Predistortion
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15 to 20 dB
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15 to 20 MHz
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12 to 14%
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High
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Medium
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Notes:
- Correction = Adjacent channel interference rejection
- Bandwidth = Bandwidth over which it can carry out linearization
- Flexibility = Ease with which it can be modified for a different spectrum
Adaptive Digital Predistortion
Predistortion requires the insertion of a nonlinear module before the RF power amplifier. The nonlinear module, called the predistorter, has the inverse response of the PA so the overall response at the output of the PA is linear. Adaptive digital predistortion involves the digital implementation of the predistorter and presence of a feedback loop (shown in Figure 1) adapting to the changes in the response of the PA due to varying operating conditions.
Figure 1. Adaptive Digital Predistortion
The two main groups of adaptation algorithms generally employed are the “blind adaptive” algorithms based on distance-gradient methods, and the “polynomial function” algorithms that attempt to directly model the nonlinearities. The correction factors computed using the adaptation algorithm are stored in a look-up table (LUT), and are dynamically updated to reduce errors between the predistorter input and the PA output.
Altera’s DPD Reference Design
This section describes the Altera® solution for an adaptive digital predistorter using the blind adaptive LUT-based approach. As seen in Figure 2, the incoming samples (I and Q) have correction factors applied from the LUT and sent to the radio frequency (RF) module. The LUT’s address is derived from the input power and the LUT contains two values for each location, the real part, I, and the imaginary part, Q. In the feedback loop, the output of the PA is downconverted—transformed to polar form—and compared with the delayed version of the input to the predistorter in polar form. This error is then used to update the values currently stored in the LUT.
Figure 2. Altera’s DPD Reference Design
The following device solutions from Altera are well-suited for implementing the blocks shown in Figure 2.
Hardware Acceleration with CORDIC
The Cartesian-polar and polar-Cartesian conversions in Figure 2 can be efficiently implemented with Altera’s coordinate rotation digital computer (CORDIC) intellectual property (IP) solution. CORDIC is an iterative algorithm that performs various trigonometric functions by using only additions, subtractions, and shift operations. The Altera® CORDIC uses logic elements (LEs) operating in “arithmetic mode,” where each LE is configured to contain a full adder or subtractor cell plus an associated register. The deeply pipelined, parallel architecture enables operating speeds at over 300 MHz.
Complex Multiplication with DSP Blocks
The application of correction factors from the LUT involves complex multiplications that map well onto the embedded digital signal processing (DSP) blocks available in Stratix® series FPGAs. Each DSP block has a number of multipliers, followed by adder/subtractor/accumulators, in addition to registers for pipelining. With these features, Stratix series FPGAs can efficiently implement complex multiplications and reduce the amount of overall logic and routing required in PA designs.
TriMatrix Memory for LUT Implementation
Stratix series FPGAs feature the TriMatrix memory structure, composed of three sizes of embedded RAM blocks, which can all be configured to support a wide range of features. Offering up to 22.4 Mbits of RAM, the TriMatrix memory structure makes Stratix IV FPGAs an ideal choice for memory-intensive applications.
Adaptive Algorithm on Nios II Embedded Processors
With the highly flexible soft embedded Nios® II processors, you can quickly modify the adaptive algorithm in software and customize your solution without getting too involved with scheduling complex datapaths. Nios II processors are soft embedded cores and can use custom instructions for hardware acceleration of program code.
Altera Solution for Memory Effect
The memory effect models the distortions due to short-term temperature variations on the silicon of the PA transistors. The temperature depends on the magnitude of current and previous input samples. Hence, you can use a finite impulse response (FIR) filter in the address calculation block to compensate for the memory effect, by providing a weighted sum of previous inputs as an index to the LUT.
The Altera Advantages for DPD
Flexibility
Systems that implement DPD must be flexible enough to adapt to the future improvements in data converter and power transistor technologies. They should also be able to support different configurations (single carrier vs. multi-carrier) and multiple standards. Altera devices provide this flexibility.
Lower Risk
The in-field-programmability feature of Altera devices significantly lowers the risk of introducing new technologies such as DPD, while also offering scalability for different types of systems (e.g., macro, micro, and pico BTSs). The remote-upgradeability feature further enhances flexibility.
Integrated Solution
The advanced architectural features of Stratix series FPGAs combined with enhanced Nios II soft embedded processors enable a highly integrated solution, including additional functionality such as crest factor reduction and digital up and down conversion.
Parameterized Solution
You can implement a custom design optimized for your application (e.g., filter skirts, decimation factor, word length) resulting in superior performance compared to a generic ASSP solution.
Cost Reduction Path
If you want to implement the DPD technique using Altera high-density FPGAs, you need a low-risk, cost-reduction path for high-volume production. To achieve this, you can migrate your design from an FPGA to a HardCopy® ASIC. HardCopy ASICs offer a migration process that supports the high-density Stratix series FPGAs and can offer up to 70 percent cost reduction.
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