With the proliferation of wireless standards—including wide area 3G, 2.5G, and local area 802.11 networks—future wireless devices will need to support multiple air-interfaces and modulation formats. Software defined radio (SDR) technology enables such functionality in wireless devices by using a reconfigurable hardware platform across multiple standards. With FPGA and data converter technology continuously evolving, the SDR concept is increasingly becoming a reality. Altera® programmable logic devices, along with a comprehensive portfolio of intellectual property (IP) cores and state-of-the-art design software, offer an ideal platform for efficiently implementing SDR technology.
SDR System Architecture
Figure 1 illustrates the hardware partitioning of an SDR-based 3G basestation that you can reconfigure to support multiple standards. To reconfigure the entire system, an ideal SDR basestation would perform all signal processing tasks in the digital domain. However, current-generation wideband data converters cannot support the processing bandwidth and dynamic range required across different wireless standards. As a result, the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC) are usually operated at intermediate frequency (IF) and separate wideband analog front ends are used for subsequent signal processing to the radio frequency (RF) stages, as shown in Figure 1.
Figure 1. SDR Architecture Based on Current-Generation Technology
- DUC: Digital upconverter
- CFR: Crest factor reduction
- DPD: Digital predistortion
- DDC: Digital downconverter
- PA: Power amplifier
- LNA: Low noise amplifier
Digital IF Processing
Digital IF extends the scope of digital signal processing (DSP) beyond the baseband domain out to the antenna to the RF domain. This increases the flexibility of the system while reducing manufacturing costs. Moreover, digital frequency conversion provides greater flexibility and higher performance (in terms of attenuation and selectivity) than traditional analog techniques. Altera Stratix® series FPGAs, with their high-performance embedded DSP blocks, Nios® II embedded soft processors, TriMatrix memory architecture, and high-speed interfaces, provide a highly flexible and integrated platform to implement computationally intensive digital IF functions including digital up-down converters, while reducing the risk involved in introducing new techniques such as DPD, CFR, and smart antennas.
Data formatting—often required between the baseband processing elements and the upconverter—can be seamlessly added at the front end of the upconverter, as shown in Figure 2. This technique provides a fully customizable front end to the upconverter and allows for channelization of high-bandwidth input data, which is found in many 3G systems. You can use custom logic or a Nios II embedded processor to control the interface between the upconverter and the baseband processing element.
Figure 2. Digital Upconverter
- RRC = Root-raised cosine
- NCO = Numerically controlled oscillator
In digital upconversion, the input data is baseband filtered and interpolated before it is quadrature modulated with a tunable carrier frequency. To implement the interpolating baseband finite impulse response (FIR) filter, Altera offers the FIR Compiler with which optimal fixed or adaptive filter architectures can be built for a particular standard through speed-area tradeoffs. Altera also offers the NCO Compiler intellectual property (IP) core that can generate a wide range of architectures for oscillators with spurious-free dynamic range in excess of 115 dB and very high performance. Depending on the number of frequency assignments to be supported, you can easily instantiate the right number of digital upconverters in a programmable logic device (PLD).
Crest Factor Reduction
3G code-division multiple access (CDMA)-based systems and multi-carrier systems such as orthogonal frequency division multiplexing (OFDM) exhibit signals with high crest factors (peak-to-average ratios). Such signals drastically reduce the efficiency of PAs used in the basestations. Altera FPGAs offer a reconfigurable platform for SDR basestations to implement CFR techniques that are customized to each standard.
The 3G standards and their high-speed mobile data versions employ non-constant envelope modulation techniques such as quadrature phase shift keying (QPSK) and quadrature amplitude modulation (QAM). This places stringent linearity requirements on the power amplifiers. DPD linearization techniques, including both look-up table (LUT) and polynomial approaches, can be efficiently implemented using Stratix series FPGAs. The multipliers in the DSP blocks can reach speeds up to 380 MHz and can be effectively time-shared to implement complex multiplications. When used in SDR basestations, you can reconfigure Stratix series FPGAs to implement the appropriate DPD algorithm that efficiently linearizes the PA used for a specific standard.
On the receiver side, digital IF techniques can be used to sample an IF signal and perform channelization and sample rate conversion in the digital domain. Using undersampling techniques, high frequency, IF signals (typically 100+ MHz) can be quantified. For SDR applications, since different standards have different chip/bit rates, non-integer sample rate conversion is required to convert the number of samples to an integer multiple of the fundamental chip/bit rate of any standard. Altera’s DSP Builder tool includes a programmable resampler block that can perform non-integer decimation with conversion ratios between 0.5 and 1.
Figure 3. Digital Downconverter
Wireless standards are continuously evolving to support higher data rates through the introduction of advanced baseband processing techniques such as adaptive modulation and coding, space-time coding (STC), beamforming, and multiple-input multiple-output (MIMO) antenna techniques. The baseband signal processing devices require enormous processing bandwidth to support such computationally intensive algorithms. Altera FPGAs are tailored for such applications with examples being channel coding for HSDPA and beamforming.
The baseband components also need to be flexible enough to enable SDR functionality that is required to support migration between enhanced versions of the same standard as well as the capability to support a completely different standard. The remote upgradeability feature using the Nios II embedded
processor, along with the availability of a wide array of IP cores make Altera FPGAs an ideal choice to enable such SDR functionality in both transmit and receive signal processing datapaths. Figure 4 shows an example scenario where Altera FPGAs can be easily reconfigured to support the baseband transmit functions for either WCDMA/HSDPA or 802.16a standards through available MegaCore® functions and reference designs such as the Reed-Solomon encoder and inverse fast Fourier transform (IFFT).
Figure 4. Example SDR baseband data path reconfiguration
As shown in Figure 5, SDR baseband processing often requires both processors and FPGAs, where the processor handles system control and configuration functions while the FPGA implements the computationally-intensive signal processing data path and control, minimizing the latency in the system. To go between standards, the processor can switch dynamically between major sections of software while the FPGA can be completely reconfigured, as necessary, to implement the data path for the particular standard.
Figure 5. Co-Processing Architecture for SDR
Altera FPGA coprocessor interface with a wide range of DSP and general-purpose processors provide increased system performance and lower system costs. Altera’s SOPC Builder, which includes an extension of the MathWorks Simulink environment, known as DSP Builder, is a robust tool to facilitate coprocessor integration. With DSP Builder, you can assemble parameterized blocks representing a plethora of functions ranging from muxes through fully parameterized FIR filters. Once a dataflow system has been captured in DSP Builder, it can be exported for use as a coprocessor in any processor-based system assembled by SOPC Builder. Using SOPC Builder’s interactive menus, you are able to set the parameters of the components they intend to use and then can choose the optimal Avalon® system interconnect to connect the selected components. In addition, you can store function blocks created using SOPC Builder for reuse in future designs, providing additional time and cost benefits.
SDR for Defense Applications
SDR is the underlying technology behind the Joint Tactical Radio System (JTRS) initiative to develop software programmable radios that can enable seamless, real-time communication across the U.S. military services, and with coalition forces and allies. The functionality and expandability of the JTRS is built upon an open architecture framework called the Software Communications Architecture. The JTRS terminals must support dynamic loading of any one of over 30 specified air interfaces or waveforms that are typically more complex than those used in the civilian sector. Altera FPGAs have the necessary processing power and flexibility to address such requirements. Altera is also a member of the SDR Forum and is actively involved in contributing to the growth of SDR technology.