UMTS Wireless Network
The universal mobile telecommunication system (UMTS) is a third-generation (3G) wireless system that delivers high-bandwidth data and voice services to mobile users. UMTS evolved from global systems for mobile communications (GSM). UMTS has a new air interface based on W-CDMA and an intellectual property (IP) core network based on general-packet radio service (GPRS). Figure 1 shows the infrastructure of a UMTS wireless network.
Figure 1. UMTS Wireless Network Infrastructure
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Voice and data transport is performed by the transport layer nodes, colored blue:
- Node B = Base transceiver station (BTS)
- RNC = Radio network controller or basestation controller (BSC)
- SGSN = Serving GPRS support node
- GGSN = Gateway GPRS support node
- MGW = Media gateway
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The call control function is mainly performed by the call control layer nodes, colored yellow:
- CSCF = Call state control function
- MGCF = Media gateway control function
- HSS = Home subscriber server
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The air interface of Node B is discussed on W-CDMA. The 3GPP website contains more information on the UMTS specifications.
Transport Layer Node Architecture
The transport layer node can be built on an asynchronous transfer mode (ATM) switch, a packet switch, or an Internet protocol router. It consists of an optional interface to call control layer nodes, host processor, adjacent node interfaces, and switch fabric. Adjacent node interfaces and switch fabric together form the voice and data path. Figure 2 shows the architecture of a generic transport layer node.
Figure 2. Transport Layer Node Architecture
In Figure 2, the two parts implemented in programmable logic are the call control layer interface and the voice and data path. The call control layer interface is the interface logic to call control layer nodes such as HSS, CSCF, and MGCF. The voice and data path uses Internet protocol to transport packet voice and data within the UMTS wireless network. Figure 3 shows a packet voice and data path implementation.
Figure 3. Packet Voice & Data Path Functional Blocks
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The main functions of the packet voice and data path implementation shown above include:
- Physical Layer Processing—The physical layer processing function processes SONET/SDH or T/E/J frame headers and extracts point-to-point protocol (PPP) packets on the receiver side. On the transmitter side, it places PPP packets into the frame payload and adds the frame header.
- Higher Layer Processing—The higher layer processing function performs parsing, framing, packet classification, and modification. Encryption and compression processors are usually supported and special processors are often used to accelerate the process. The queuing and traffic manager function places packets on different priority queues and drops packets according to the traffic condition.
- Switching—The switch fabric performs switching and routing functions for voice and data. It also contains a queue manager.
- Control and Management—The control and management function performs path control and collects data for management purposes.
Altera & AMPPSM IP Cores
The following IP cores are available on the IP MegaStore™ website:
The Altera Advantage
Using Altera® products for 3G wireless networks offer the advantages listed below.
Time-to-Market
The 3G wireless network market is very competitive, which makes time-to-market particularly important. Using Altera FPGAs and IP cores saves vital time, since designers no longer have to wait for the turnaround times necessary for ASIC development.
Flexibility
Because the migration to 3G will require multiple revisions and will not occur in one step, ASICs are not a viable platform. Altera's FPGA solution provides the flexibility to implement new proprietary features and perform remote in-field upgrades.
Embedded DSP Blocks
Stratix® II digital signal processing (DSP) blocks consist of hardware multipliers, adders, subtractors, accumulators, and pipeline registers. The DSP blocks are flexible, efficient, and optimized for a variety of DSP applications requiring high data throughput, which makes DSP blocks ideal for wireless communications.
High-Bandwidth Differential I/O Support
Altera Stratix II devices with differential I/O (LVDS and HyperTransport™) support allow designers to meet their high-bandwidth needs with up to 152 receiver and 156 transmitter channels operating at up to 1 Gbps per channel.
Nios II Embedded Processor Solutions
The Nios® II embedded processor is based on the highly successful and revolutionary concept of embedding soft embedded core RISC processors within FPGAs. The advanced architectural features of Stratix II FPGAs, combined with the Nios II embedded processor, offer unparalleled processing power to meet the needs of high-bandwidth systems.
Clock Data Recovery
Clock data recovery (CDR) is useful when the data rate is high. Altera Stratix GX devices include dedicated CDR circuitry and can recover 20 clock channels at a 3.125 Gbps data rate.
Quartus II Software
When combined with Altera IP cores and the library of parameterized modules (LPM), Quartus® II development software makes the design process even faster and easier. LPM functions can be plugged into a design directly, and most can be accessed through the MegaWizard® Plug-In user interface and customized with just a few clicks.
Cost-Reduction Path
System designers implementing wireless applications using Altera high-density FPGAs may need a low-risk cost-reduction path for high-volume production. Those designers can migrate their designs from an FPGA to a HardCopy® II structured ASIC. For example, time-sensitive wireless applications can be prototyped and ramped up into production using Altera FPGAs, and when the design is ready for high-volume production, the design can be migrated to HardCopy II structured ASICs, thus reducing overall costs.
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