The universal mobile telecommunication system (UMTS) is a 3G wireless system that delivers high-bandwidth data and voice services to mobile users. UMTS evolved from global systems for mobile communications (GSM). UMTS has an air interface based on W-CDMA and an Internet protocol core network based on general-packet radio service (GPRS). Figure 1 shows the infrastructure of a UMTS wireless network.
Figure 1. UMTS Wireless Network Infrastructure
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Voice and data transport is performed by the transport layer nodes, colored blue:
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The call control function is mainly performed by the call control layer nodes, colored yellow:
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The air interface of node B is discussed on W-CDMA. The 3GPP website contains more information on the UMTS specifications.
Transport Layer Node Architecture
The transport layer node can be built on an asynchronous transfer mode (ATM) switch, a packet switch, or an Internet protocol router. It consists of an optional interface to call control layer nodes, host processor, adjacent node interfaces, and switch fabric. Adjacent node interfaces and switch fabric form the voice and data path. Figure 2 shows the architecture of a generic transport layer node.
Figure 2. Transport Layer Node Architecture
In Figure 2, the two parts implemented in programmable logic are the call control layer interface and the voice and datapath. The call control layer interface is the interface logic to call control layer nodes such as HSS, CSCF, and MGCF. The voice and datapath uses the Internet protocol to transport packet voice and data within the UMTS wireless network. Figure 3 shows a packet voice and data path implementation.
Figure 3. Packet Voice and Data Path Functional Blocks
The main functions of the packet voice and data path implementation shown in Figure 3:
- Physical layer processing—The physical layer processing function processes SONET/SDH or T/E/J frame headers and extracts point-to-point protocol (PPP) packets on the receiver side. On the transmitter side, it places PPP packets into the frame payload and adds the frame header.
- Higher layer processing—The higher layer processing function performs parsing, framing, packet classification, and modification. Encryption and compression processors are usually supported and special processors are often used to accelerate the process. The queuing and traffic manager function places packets on different priority queues and drops packets according to the traffic condition.
- Switching—The switch fabric performs switching and routing functions for voice and data. It also contains a queue manager.
- Control and management—The control and management function performs path control and collects data for management purposes.
Altera and AMPP IP Cores
The following intellectual property (IP) cores are available on the IP MegaStore™ website:
- SONET/SDH Framers
- T/E Framer
- PPP Packet Processor
- POS-PHY Level2/3
- ATM Cell Processor
- UTOPIA Level2/3
- DES Encryption Core
- MD5, SHA-1 Hash Functions
- SDRAM Controller
The Altera Advantage
Using Altera® products for 3G wireless networks offers many advantages.
Time-to-Market
The 3G wireless network market is very competitive, which makes time-to-market particularly important. Using Altera FPGAs and IP cores saves vital time, since you no longer have to wait for the turnaround times necessary for ASIC development.
Flexibility
Because the migration to 3G requires multiple revisions and does not occur in one step, ASICs are not a viable platform. Altera's FPGA solution provides the flexibility to implement new proprietary features and perform remote in-field upgrades.
Embedded DSP Blocks
Stratix® series high-performance digital signal processing (DSP) blocks consist of hardware multipliers as well as registers, adders, subtractors, accumulators, and summation unit-functions that are frequently required in typical DSP algorithms. The DSP block supports completely variable bit-widths and various rounding and saturation modes to efficiently meet the exact requirements of your application. The DSP blocks are flexible, efficient, and optimized for a variety of DSP applications requiring high data throughput, making DSP blocks ideal for wireless communications.
Unprecedented System Bandwidth
Stratix series high-performance products now offer new levels of system bandwidth support:
- High-speed transceivers rates up to 8.5 Gbps
- 1,067 Mbps (533 MHz) DDR3 memory interfaces
- 550-MHz DSP performance through parallelism with optimal DSP/memory/logic ratio
- 600-MHz TriMatrix memory blocks
- 1.6-Gbps LVDS channels
- 600-MHz core clock speeds
Nios II Embedded Processor Solutions
The Nios® II embedded processor is based on the highly successful and revolutionary concept of embedding soft embedded core RISC processors within FPGAs. The advanced architectural features of Altera FPGAs and HardCopy® ASICs, combined with the Nios II embedded processor, offer unparalleled processing power to meet the needs of high-bandwidth systems.
Quartus II Software
When combined with Altera IP cores and the library of parameterized modules (LPM), Quartus® II development software makes the design process even faster and easier. LPM functions can be plugged into a design directly, and most can be accessed through the MegaWizard® Plug-In Manager and customized with just a few clicks.
Cost-Reduction Path
If you implement wireless applications using Altera high-density FPGAs, you may need a low-risk cost-reduction path for high-volume production. You can migrate your designs from an FPGA to a HardCopy® ASIC. For example, time-sensitive wireless applications can be prototyped and ramped up into production using Altera FPGAs, and when the design is ready for high-volume production, the design can be migrated to HardCopy ASICs, thus reducing overall costs.
