W-CDMA Channel Card
The International Telecommunications Union (ITU), under the IMT-2000 initiative devised standards that support multimedia and high-speed data services. W-CDMA was chosen as a next-generation access for global-system-for-mobile-communication technology.
For a detailed discussion on W-CDMA implementation with Altera® solutions, refer to AN: 129 Implementing a W-CDMA System.
Baseband Transmitter
This section describes the digital architecture of a downlink transmitter that supports the W-CDMA standard. Figure 1 shows a block diagram of the transmitter. Blue blocks can be implemented in an Altera FPGA; orange blocks can be implemented in software in the Nios® II embedded processor.
Figure 1. Transmitter Architecture
Click the image for a larger view and more information
To conform to the W-CDMA standard, cyclic redundancy check bits are added for error detection, and error correction bits are added for channel coding. The data is then spread with a user- or channel-specific code to produce a datastream at a given chip-rate. The spread data stream is scrambled with Gold code so that multipath signals can be uniquely identified and decoded by the receiver. To transmit a signal within the specified bandwidth, the data bits are shaped using a pulse-shaping filter. Next, the signal goes through carrier modulation and up-conversion to radio frequency (RF), and is then sent to the antenna to be transmitted over the air.
Baseband Receiver
This section describes the digital architecture of a receiver that supports the W-CDMA standard. Figure 2 shows a block diagram. Blue blocks can be implemented in an Altera FPGA; orange blocks can be implemented in software in the Nios II embedded processor.
Figure 2. Receiver Architecture
Click for a larger view and more information
Altera & AMPP IP Cores
The following cores are available in the Altera IP MegaStore™ web site:
Altera Advantages
Altera provides the following advantages for W-CDMA applications.
Flexibility
Systems that implement the W-CDMA standard must be flexible enough to accommodate changes with the standard, as well as improvements in capacity enhancement techniques such as adaptive antenna and multi-user detection schemes. FPGAs provide this flexibility.
NRE Cost
Because the demand for third-generation (3G) systems cannot be accurately predicted, it is difficult to justify the high non-recurring engineering (NRE) costs associated with ASICs when developing a system. Altera HardCopy® II structured ASICs are a low-cost, time-saving alternative to ASICs for high-volume production. HardCopy II structured ASICs are ideal for customers who need a low-risk cost reduction path to volume production for their W-CDMA systems.
Processing Speed
W-CDMA signal processing requirements go beyond the capability of generic digital signal processors. You can use the programmable Stratix® II architecture to implement dedicated hardware functionality and achieve the required system speeds. Also, the high-density Stratix II devices let users replicate hardware functionality to support multiple channels.
Logic/Processor Solution
W-CDMA demands fast signal processing, which requires logic implementation. However, these applications also have complex control algorithms such as searching, multipath tracking, and finger assignment, which are better-suited for implementation in software. With the Altera Nios II embedded soft processor, users can integrate both hardware and software system functions on a single chip, eliminating I/O bottlenecks that limit system performance.
Comprehensive Core Portfolio
Altera provides a comprehensive solution for baseband signal processing as well as for network interface. Details on the network interface-related cores are contained on the UMTS Wireless Network page.
Cost-Reduction Path
System designers who implement telecommunications applications using Altera high-density FPGAs need a low-risk, cost-reduction path for high-volume production. To achieve this cost reduction, designers can migrate their designs from an FPGA to a HardCopy II structured ASIC. HardCopy II structured ASICs offer a migration process from high-density Stratix II devices. For example, time-sensitive telecommunications applications can be prototyped and initially produced using Stratix II devices, and when the design is ready for high-volume production, system designers can reduce overall costs by migrating their designs to HardCopy II structured ASICs.
Related Links
|
Literature
> 
