The International Telecommunications Union (ITU), under the IMT-2000 initiative devised standards that support multimedia and high-speed data services. W-CDMA was chosen as a next-generation access for global-system-for-mobile-communication technology.
Baseband Transmitter and Receiver
Figure 1 shows a block diagram of a downlink transmitter that supports the W-CDMA standard. The blue blocks can be implemented in an Altera® FPGA; orange blocks can be implemented in software in the Nios® II embedded processor.
Figure 1. Transmitter Architecture
To conform to the W-CDMA standard, cyclic redundancy check bits are added for error detection, and error correction bits are added for channel coding. The data is then spread with a user- or channel-specific code to produce a datastream at a given chip rate. The spread data stream is scrambled with Gold code so that the receiver can uniquely identify and decode the multipath signals. To transmit a signal within the specified bandwidth, the data bits are shaped using a pulse-shaping filter. Next, the signal goes through carrier modulation and upconversion to radio frequency (RF), and is then sent to the antenna to be transmitted over the air.
Figure 2 shows a block diagram of a receiver that supports the W-CDMA standard. The blue blocks can be implemented in an Altera FPGA; orange blocks can be implemented in software in the Nios II embedded processor.
Figure 2. Receiver Architecture
Altera and AMPP IP Cores
The following cores are available in the Altera IP MegaStore™ web site:
- Viterbi Decoder
- Finite Impulse Response (FIR) Compiler
- Numerically Controlled Oscillator (NCO) Compiler
Altera Advantages
Altera provides many advantages for W-CDMA applications.
Flexibility
Systems that implement the W-CDMA standard must be flexible enough to accommodate changes with the standard, as well as improvements in capacity enhancement techniques such as adaptive antenna and multi-user detection schemes. FPGAs provide this flexibility.
Processing Speed
W-CDMA signal processing requirements go beyond the capability of generic digital signal processors. You can use the programmable high-performance Stratix® series and midrange Arria® GX series architecture to implement dedicated hardware functionality, supporting multiple channels and achieving the required system performance.
Logic/Processor Solution
W-CDMA demands fast signal processing, which requires logic implementation. However, these applications also have complex control algorithms such as searching, multipath tracking, and finger assignment, which are better-suited for implementation in software. With the Altera Nios® II embedded soft processor, you can integrate both hardware and software system functions on a single chip, eliminating I/O bottlenecks that limit system performance.
Comprehensive Core Portfolio
Altera provides a comprehensive solution for baseband signal processing and network interfacing. Details on the network interface-related cores are contained on the UMTS Wireless Network page.
Cost-Reduction Path
If you implement telecommunications applications using Altera high-density FPGAs, you need a low-risk, cost-reduction path for high-volume production. To achieve this cost reduction, you can migrate your design from an FPGA to a HardCopy® ASIC. HardCopy ASICs offer a migration process from high-density Stratix series FPGAs. For example, time-sensitive telecommunications applications can be prototyped and initially produced using Stratix series FPGAs, and when the design is ready for high-volume production, you can reduce overall costs by migrating your design to HardCopy ASICs.
Low-NRE Cost-Reduction Path
Because the demand for 3G systems cannot be accurately predicted, it is difficult to justify the high NRE costs associated with ASICs when developing a system. Altera’s unique HardCopy ASIC technology provides OEMs a low-risk, low-NRE, and time-saving cost reduction path to volume production for W-CDMA systems.
