LTE Channel Card Solutions
With 3rd Generation Partnership Project (3GPP) long term evolution (LTE) data rates exceeding 100 Mbps and employing complex multiple-input, multiple-output (MIMO)/space division multiple access (SDMA) techniques, LTE PHY layer implementation requires a high-performance, scalable silicon platform. Figure 1 shows a potential system partitioning between off-the-shelf digital signal processors and FPGAs that not only cost effectively addresses the processing requirements, but also provides a measure of future proofing via support for in-field programmability. View the DSP-FPGA System Partitioning for MIMO-OFDMA Wireless Basestations white paper (PDF) for more details on system partitioning options.
Figure 1. FPGA and DSP System Partitioning for LTE PHY Layer Implementation
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Notes:
- FEC = forward error correction
- IFFT = inverse fast Fourier transform
- CFR = crest-factor reduction
- CE = channel estimation
- CEq = channel equalization
- CFO = carrier frequency offset
Design for Volume
With the increasing price reduction pressure from mobile operators, basestation OEMs must design for volume from the beginning. The combination of Altera’s high-performance, lowest power Stratix® series FPGAs and HardCopy® ASICs provide OEMs a high degree of confidence and a unique opportunity to design for volume from inception, while avoiding time consuming and risky ASIC conversions. Stratix series FPGAs provide an effective mix of on-chip memory and high-performance signal processing capability to achieve the lowest cost-per-channel in next-generation LTE channel card designs. With unique low power consumption features such as Programmable Power Technology and selectable core voltage, Stratix series FPGAs provide significantly higher performance-to-power ratio than state-of-the art digital signal processors. The high-density Stratix series FPGAs also provides unprecedented levels of integration, enabling a roadmap to single chip baseband system-on-a-chip (SoC) solutions, with further cost, size, and power consumption reduction via risk-free seamless migration to HardCopy ASICs. Altera’s Arria® GX and Cyclone® FPGAs provide an unprecedented combination of power, functionality, and cost required for LTE pico basestations and remote radio heads (RRH) or for other bridging or coprocessing solutions.
Design with Agility
OEMs can design with agility by leveraging a wide variety of LTE-related intellectual property (IP) and reference designs, software development tools, and development boards provided by Altera and ecosystem partners. LTE IP and reference designs include:
LTE IP and reference designs complement Altera’s WiMAX portfolio of solutions and are highly optimized for use on Altera® silicon fabrics. OEMs can quickly leverage and integrate these building blocks with easy-to-use software tools and focus their time and efforts on differentiating their solutions. This combination of software and hardware programmability provides significantly higher flexibility than fixed architecture off-the-shelf digital signal processors and enables OEMs to quickly develop customized chipsets to meet LTE price and performance requirements.
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