LTE RF Card Solutions

With channel bandwidth increasing up to 20 MHz and the requirement for multiple sector, multiple antenna multiple-input multiple-output (MIMO) configurations, implementation of RF card functions requires a high-performance, power efficient scalable silicon platform. Sample rate converter (SRC) blocks such as digital upconverter (DUC), digital downconverter (DDC), crest-factor reduction (CFR), and digital predistortion (DPD) blocks can be implemented efficiently on FPGAs. Figure 1 shows an FPGA-based implementation that not only cost effectively addresses the processing requirements, but also provides a measure of future proofing via support for in-field programmability.

Figure 1. FPGA-Based Implementation of RF Card Functionality

Figure 1. FPGA-Based Implementation of RF Card Functionality

Notes:

O&M = operation and maintenance
CPRI = Common Public Radio Interface
OBSAI = Open Base Station Standard Initiative

Design for Volume

With the increasing price reduction pressure from mobile operators, basestation OEMs must design for volume from the beginning. The combination of Altera's high-performance, lowest power Stratix^® series FPGAs and HardCopy^® ASICs provide OEMs a high degree of confidence and a unique opportunity to design for volume from inception, while avoiding time consuming and risky ASIC conversions. Stratix series FPGAs provide an effective mix of on-chip memory and high-performance signal processing capability to achieve the lowest cost-per-channel in next-generation LTE RF card and remote radio head (RRH) designs. RRH designs have very stringent size and weight requirements, and the lack of forced airflow places a challenging requirement in terms of power consumption. With unique low power consumption features such as Programmable Power Technology and selectable core voltage, Stratix series FPGAs meet these allowable power consumption levels. The high density of Stratix series FPGAs also provides unprecedented levels of integration, enabling single-chip solutions for multiple antenna-based systems, with further cost, size, and power consumption reduction via risk-free seamless migration to HardCopy ASICs. Altera's Arria^® GX and Cyclone^® FPGAs provide an unprecedented combination of power, functionality, and cost required for LTE pico basestations and RRH designs.

Design with Agility

OEMs can design with agility by leveraging intellectual property (IP) and reference designs, software development tools, and development boards provided by Altera and ecosystem partners. Altera's intermediate frequency (IF) Modem initiative enables OEMs to quickly design highly efficient and customized multi-channel DUC and DDC functions by leveraging the easy-to-use DSP Builder software tool and cascaded integrator comb (CIC) compiler. You can use Altera’s Nios^® II soft processor to configure the DUC and DDC to support the various channel bandwidths up to 20 MHz. The Nios II processor can also handle all the initialization, configuration, status monitoring, and operation and maintenance functionality over Ethernet and RS-232 interfaces. The RF card operations and firmware can be controlled and updated remotely over a fiber link in an RRH configuration. you can easily modify Altera’s baseband CFR reference design modified to support implementation on the RF card. OEMs can also leverage Altera's QRD-RLS reference design for DPD implementations. Alternatively, you can use another instance of the Nios II processor to implement similar algorithms in software. The LTE IP and reference designs complement Altera's WiMAX portfolio of solutions and are highly optimized for use on Altera^® silicon fabric. OEMs can quickly integrate these building blocks using easy-to-use software tools and deliver customized chipsets designed to meet their LTE basestation specifications.

LTE RF Card Solutions

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Design for Volume

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