Packet processing is an area of innovation and focus for OEMs. Altera continues to enable you to meet market requirements for Wireline infrastructure. Altera offers a silicon platform based on leading-edge process technology for high-performance packet processing and provides an option for you to either make your own network processing unit (NPU) or buy a pre-built NPU that is customizable for your target application.
Altera’s Wireline ecosystem offers OEMs a comprehensive portfolio of intellectual property (IP), reference designs, and standards compliant with off-the-shelf, shrink-wrapped solutions that meet service provider requirements. Altera and its packet processing ecosystem offer OEMs a wide array of packet processing solutions to support make or buy decisions.
Buy An NPU
Altera and its partners provide turnkey packet processing solutions. As shown in Figure 1, this turnkey solution is a ready-to-use packet processor on Altera silicon from one of our partners that is optimized for a target application. It is comprised of shrink-wrapped IP that includes an application programming interface (API) and software development kit (SDK). Unlike conventional NPUs, ready-made NPUs from Altera’s partners offer OEMs a unique combination of hardware customizability and quick time to market.
Figure 1. Ready made NPU
TPACK offers Carrier Ethernet / MPLS-TP packet processing and traffic management solutions via their TPX packet transport switch family. The TPX devices provide extensive hardware-based support for OAM and synchronization, simultaneous and deterministic support of MEF E(V)PL, E(VP)-LAN and E(VP)-Tree services based on packet transport protocols such as MPLS-TP/T-MPLS and Ethernet Q-in-Q and MAC-in-MAC including advanced traffic management up to 40 Gbps throughput.
Make An NPU
Making an NPU offers you the option to control, own, and scale your packet processing roadmap. With Altera’s packet processing framework, you map the chip to the application and not the application to the chip. This allows you to optimally partition your algorithm between hardware and software. By retaining part of your algorithm in software, you can maintain programmability when you move to HardCopy and make modifications in less time than you can using complex state machines implemented in RTL.
To offer you this ability to assemble and make your own packet processor, Altera has developed a packet processing framework as shown in Figure 2. The packet processing framework includes C-programmable multi-threaded processing elements, hardware accelerators, tools for interconnect creation and hardware/software design space exploration, and a debug environment that includes the capability to do single stepping across multiple threads. By adopting this framework, you can standardize on an approach that encourages design reuse and scalability of your NPU architecture. Scalability comes from the ability to moderate performance by trading off functionality between hardware processing elements or software processing elements, adding or removing software programmable cores as needed and moving across low cost Cyclone, midrange Arria or high end Stratix series FPGAs.
Figure 2. Altera packet processing framework
Please contact your local Altera sales representative regarding Altera’s packet processing framework.
