Ethernet MACs
Altera provides a wide range of configurable 10/100 Mbps, 10/100/1000 Mbps, 10-Gbps local area network (LAN) PHY, 10-Gbps wide area network (WAN) PHY Ethernet media access controllers (MACs), physical coding sublayer (PCS) blocks, multi-port 1-Gb Ethernet switch modules, and TCP/IP acceleration solutions used in FPGAs and structured ASIC designs. These high-level, pre-packaged, proven silicon intellectual property (IP) cores and reference designs are compatible with various Ethernet standards including: 802.3, 802.1Q, 803.3ae, and 802.3ah.
Altera offers a silicon proven 10-Gigabit MAC with built-in support for the XGMII, XAUI, XSBI (64/66b PCS layer) interfaces, OC-192 support, flow control, MII management, address-based filtering, and statistics counters for Remote Network Monitoring (RMON) and Simple Network Management Protocol (SNMP). The 10-Gbps Ethernet MAC layer and reconciliation sub-layer core is compliant with the IEEE 802.3ae specification and supports multiple custom switch fabric enhancements to interface Altera® Stratix® IV GX FPGAs directly to several 10G Ethernet switch devices (see Figure 1).
Figure 1. 1G & 10G Ethernet MAC with Integrated PCS Block Diagram
Altera’s Stratix IV GX FPGAs are equipped with built-in transceivers that allow integration of various PHY interfaces and MACs into a single FPGA. Embedded within this Stratix IV GX transceiver are dedicated rate-matching first-in first-out (FIFO) buffers, 8B/10B encoding and decoding functions, and word alignment functions optimized for Ethernet applications.
The 10/100/1000 Ethernet MAC layer cores are designed to the IEEE 802.3 standard, support automated pause frame handling, IEEE 802.1q VLAN tagged frames, and jumbo frames though optional configuration register bits. Several parallel (GMII, RGMII, RMII, TBI, and RTBI) and serial (SGMII, SMII) PHY interfaces are supported allowing flexible interconnection to any optical and copper link technology with Altera Cyclone® III and Stratix IV FPGAs and HardCopy® IV ASICs (see Figure 2).
Figure 2. 1G Ethernet MAC with External PCS Block Diagram
Table 1 summarizes the IP MAC and PHY cores available for Altera devices.
| Table 1. Ethernet IP Core Supported in Altera Devices |
| IP Cores |
Vendor |
PDF |
Device Supported |
| 10/100 Mbps Solutions |
| 8B/10B Encoder/Decoder |
Altera Corporation |
 |
Cyclone II, Stratix II, Cyclone, Stratix, Stratix GX, MercuryTM, APEXTM II, APEX 20KE, APEX 20KC |
| Triple-Speed Solutions |
| 10/100/1000 Ethernet MAC |
Altera Corporation |
-
|
Cyclone, Stratix, Stratix GX |
| 10/100/1000 Ethernet MAC-Net |
MorethanIP |
- |
Cyclone, Stratix, Stratix GX |
| 10 Gigabit Ethernet Solutions |
| 10 Gigabit Ethernet MAC |
MorethanIP |
- |
APEX II, Stratix, Stratix II |
| 10 Gigabit Ethernet Physical Coding Sublayer (PCS) |
MorethanIP |
- |
- |
| Switching Solutions |
| Ethernet Layer 2 Switch |
MorethanIP |
- |
Cyclone II, Stratix II |
| 10 Gigabit Ethernet to SONET OC-192 MUX |
Nuvation |
- |
APEX II, Stratix II |
| 2 Gigabit Ethernet to SONET OC-48 MUX |
Nuvation |
- |
Cyclone II, Stratix II, Cyclone, Stratix |
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