Fabric Interface
The system backplane switch fabric forms the cental interconnect architecture for all enterprise, access, and edge networking systems. As backplane performance increases from 40 Gbps to 160 Gbps to 320 Gbps, special care must but taken to insure the interface between the switch fabric and its traffic source does not become a system bottleneck. The fabric interface must stream traffic efficiently from 2.5 Gbps to 10+ Gbps with good signal integrity while supporting key fabric requirements such as data throughput, flow control, and pre-flow queuing. Figure 1 shows a block diagram of a typical fabric interface controller (FIC).
Figure 1. Fabric Interface Controller Block Diagram
Notes to Figure 1:
- NPU = Network Processing Unit
- VOQ = Virtual Output Queue
- CSIX = Common Switch Interface
Solution Overview
Altera® Stratix® GX and Stratix II GX FPGAs with embedded multi-gigabit transceivers provide an ideal platform for developing FICs for a wide range of mesh, star, and dual-star fabric topologies. Altera developed an advanced telecom computing architecture (ATCA) reference design platform to accelerate the design and development of 2.5 Gbps and 10 Gbps FIC bridge designs.
Figure 2. ATCA Reference Design Platform
The ATCA FIC module is a flexible, cost-effective board using an Altera Stratix GX EP1SGX40 device for developing FIC designs and an Altera Stratix EP1S80 FPGA for developing traffic management and/or enhanced traffic generation and monitoring functions for performance testing and system diagnostics. The FIC board shown in Figure 3 is designed to fit in the fabric mezzanine slot on the Intel ATCA-compliant IXMB2400 dual network processor base card. To find out more about Altera’s ATCA fabric interface controller solution, contact your local Altera sales representative.
Figure 3. Altera 10 Gbps Fabric Interface Controller Board
Bridging NPU & Switch Fabric Interfaces
The fabric interface controller shown in Figure 3 fits between the NPU and switch fabric devices. The NPU interface could be reprogrammed to support SPI-4.2, CSIX, or other proprietary packet processing interfaces. The switch fabric interface is driven by the high-speed Stratix GX transceivers which operate between 1 and 3.125 Gbps. The switch fabric interface could be programmed to support many switch fabric protocols including XAUI, PCI-Express, Advanced Switching, Serial Rapid I/O, or proprietary switch fabric protocols. The Altera Atlantic on-chip bus interconnect standard allows designers to easily mix and match a variety of NPU and switch fabric interfaces for customizing fabric interface controller solutions.
Virtual Input & Output Queue Management
Memory is required to buffer packets, perform rate matching, and to provide separate input and output queues to help eliminate head-of-line blocking in switch fabrics. The internal M-RAMs within the Stratix, Stratix GX, Stratix II, and Stratix II GX families provide an ideal solution for packet buffers and virtual output queues.
At 10-Gbps speeds, buffering and control memories are stored in external memories. Stratix II families support high-speed DRAM interfaces such as RLDRAM II and DDR2, as well as high-speed SRAM interfaces such as QDR II. To reduce system cost, designers can target DRAMs for the external memories, as opposed to expensive SRAM memories. The access limitations of DRAM technologies may require caching of queue information in SRAMs. Altera’s M-RAM blocks can also be used to store caching information on-chip, reducing latency and total system costs.
Features & Benefits
- Altera Stratix GX and Stratix II GX transceivers are ideal for 1- to 6.25-Gbps backplane interface applications and conform to XAUI, PCI-Express/Advanced Switching, Serial-Rapid I, and other jitter tolerance, transfer, and generation parameters. Stratix GX transceivers include up to 24 SERDES for use in many differnet mesh, star, and dual-star backplane interface topologies.
- Altera Stratix GX, Stratix II, and Stratix II GX dynamic phase alignment (DPA) interfaces support up to 1000-Mbps LVDS data rates and comply with the Optical Internetworking Forum (OIF) specifications for high-speed system packet interface (SPI-4.2). These devices also comply with the Optical Internetworking Forum (OIF) specifications for high-speed physical layer interface (SFI4 – 10Gbps SERDES/Framer Interface).
- Stratix II devices offer up to 9 Mbits of embedded TriMatrix™ memory to address the memory caching required by 10-Gbps traffic managers. In addition to the embedded memory, Stratix II devices also offer extensive support for various advanced memory interfaces, for example, DDR II, RLDRAM II and QDR II.
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